QCLINUX: arm64: configs: qcom: enable core crypto hash and SHA-256 op… - #901
Open
Sasi Kumar Maddineni (sasikuma-qti) wants to merge 528 commits into
Open
Sasi Kumar Maddineni (sasikuma-qti) wants to merge 528 commits into
Sasi Kumar Maddineni (sasikuma-qti) wants to merge 528 commits into
Conversation
Qualcomm Glymur SoC has two Camera Control Interface (CCI) controllers. Each controller contains two I2C hosts. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Define pinctrl definitions to enable camera master clocks on glymur. Signed-off-by: Nihal Kumar Gupta <nihalkum@qti.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Define ov08x40 on cci1_i2c1. The RGB sensor is connected to CSIPHY4 in four lane mode. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…glymur Add an IMEM on glymur which falls back to mmio-sram and define the PIL relocation info region as its child, for post mortem tools to locate the loaded remoteprocs. Link: https://lore.kernel.org/lkml/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com/#r Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Without this property the scheduler treats all cores as equal. Values derived from performance measurements at 825.6 MHz: - M-class cores (cpu0-cpu5, oryon-2-2): capacity-dmips-mhz = 1024 - L-class cores (cpu6-cpu17, oryon-2-1): capacity-dmips-mhz = 1372 Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/all/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Glymur SoC. Unlike the CRD, the QCB exposes the board in a form factor suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add initial device tree support for it. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The Mahua QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Add a compatible for this board. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add initial device tree support for the Mahua QCB. The QCB (Qualcomm Compute Board) is a board built on the Qualcomm Mahua SoC, a 12-core variant of the Glymur QCB in an open form factor. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Link: https://lore.kernel.org/all/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com/ Reviewed-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vinayak.katoch@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for glymur-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for mahua-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Unlike the CPU, the CDSP does not throttle its speed automatically when it reaches high temperatures in lemans. Set up CDSP cooling for both instances by throttling the cdsp, when it reaches 105°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-qmi-tmd-v3-5-291a2ff4c634@oss.qualcomm.com
…bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Add support for IRIS on lemans when Linux host running at EL2. Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
… controller Add the "wakeup-source" property to the primary port controller node so its interrupt can wake the system from low‑power states on lemans EVK platform. Link: https://lore.kernel.org/all/20260215183325.3836178-3-swati.agarwal@oss.qualcomm.com/ Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Switch the iris video codec node in sa8775p (lemans) from the legacy 'iommus' property to 'iommu-map', using IRIS_NON_PIXEL_VCODEC and IRIS_PIXEL function IDs to identify the non-pixel and pixel context bank SMMU stream mappings respectively. Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
As per memory map, video firmware memory region is 7MB for sa8775* variants while it is 16MB for qcs9100* variants. Keeping the 7MB variant of video firmware in ride common DTS does not allow qcs9100* to pick the 16MB variant. Drop it from common and define in respective variant DTS. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Venkata Siva Pavan KumarVenkatapatigari <venvenk@qti.qualcomm.com>
…r primary port controller Rename the hd3ss3220_ instance to improve clarity and simplify usage when adding a secondary port controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260406110113.1709886-2-swati.agarwal@oss.qualcomm.com
…er in host mode
Enable secondary USB controller in host mode on lemans EVK Platform.
Secondary USB controller is connected to a Genesys Logic USB HUB GL3590
having 4 ports. The ports of hub that are present on lemans EVK standalone
board are used as follows:-
1) port-1 is connected to HD3SS3220 Type-C port controller.
2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART
for Bluetooth. This port is to be used only if user optionally replaces the
WiFi card with the NFA765 chip which uses USB for Bluetooth.
Remaining 2 ports will become functional when the interface plus mezzanine
board is stacked on top of corekit:
3) port-2 is connected to another hub which is present on the mezz through
which 4 type-A ports are connected.
4) port-3 is used for the M.2 B key for a 5G card when the mezz is
connected.
Secondary USB Controller
↓
GL3590 USB Hub (4 ports)
|
|-- Port 1 → HD3SS3220 Type‑C Port Controller → USB‑C Connector
|
|-- Port 2 → Mezzanine USB Hub (when mezz attached)
|
|-- Port 3 → M.2 B‑Key Slot (when mezz attached)
|
|-- Port 4 → M.2 E‑Key Slot
(Default: BT via UART;
USB only if NFA765 module is installed)
Mark the second USB controller as host only capable and add the HD3SS3220
Type-C port controller along with Type-C connector for controlling vbus
supply.
Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260406110113.1709886-3-swati.agarwal@oss.qualcomm.com
…oller Enable the tertiary usb controller connected to micro usb port in OTG mode on Lemans EVK platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260306091355.1178333-5-swati.agarwal@oss.qualcomm.com
Add dailinks for DISPLAY-PORT to enable audio functionality on edp0. Link: https://lore.kernel.org/all/20260413043713.1659-1-kumar.singh@oss.qualcomm.com/ Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
The lemans EVK board supports either eMMC or SD-card, but only one can be active at a time. Move the SDHC node for SD card into a dedicated device tree overlay. This decoupling allows the storage medium to be selected dynamically by applying the appropriate overlay for either SD card or eMMC support. Link: https://lore.kernel.org/all/20260227102405.2339544-2-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
…a overlay Enable the SDHCI controller for eMMC functionality on the lemans EVK using a device tree overlay. Configure the corresponding addresse space and resources for eMMC. Link: https://lore.kernel.org/all/20260227102405.2339544-3-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Add AEST RAS error source nodes for the Lemans SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/lkml/20260505-aest-devicetree-support-v1-7-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
…no SMMU On Lemans platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-4-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable the IXGBE and IXGBEVF drivers to support the Intel X550 T2 NIC on QLI boards with SR-IOV support. Signed-off-by: Hariprasad kelam <kelam@qti.qualcomm.com>
The Shikra EVK boards have an RGMII TI PHY connected to the dual EMACs of the SoC. Remove its config from prune.config to enable its driver. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the extensible scheduling class (SCX) which allows BPF-based scheduling policies. Also enable its cgroup dependencies: - CONFIG_SCHED_CLASS_EXT=y -- core sched_ext class BTF support (DEBUG_INFO_BTF, DEBUG_INFO_BTF_MODULES) is enabled which is required by SCHED_CLASS_EXT and also needed for BPF CO-RE and kernel module BTF. Signed-off-by: Ashay Jaiswal <ashay.jaiswal@oss.qualcomm.com>
…a SoC Enable the video, camera and gpu clock controllers for their respective functionalities on the Qualcomm Eliza boards. Link: https://lore.kernel.org/r/20260317-eliza_mm_clock_controllers_v1-v1-7-4696eeda8cfb@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Enable CONFIG_DMA_CMA as a dependency to allow the DMA-BUF heap configs (DMABUF_HEAPS, DMABUF_HEAPS_CMA, DMABUF_HEAPS_SYSTEM) to be selected in qcom.config. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
This reverts commit 2549688. These changes are superseded by the BCL v2 patch series. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Enable Qualcomm pmic BCL driver config. Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com>
Enable CONFIG_XDP_SOCKETS to support AF_XDP zero-copy networking on Qualcomm platforms. AF_XDP provides a high-performance path for packet processing by allowing XDP programs to redirect frames directly to userspace via shared memory rings, bypassing the normal kernel network stack. Signed-off-by: Rajkumar Patel <patel.rajkumar@oss.qualcomm.com>
…emory and SMMU mappings" This change have introduced an issue on multimedia builds where AudioRecord is broken on monaco-evk board. [ 153.325884] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to start APM port 19 [ 153.335982] q6apm-lpass-dais 3000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC error (-110): at soc_dai_trigger() on SEC_MI2S_TX [ 153.348489] MultiMedia2 Capture: ASoC error (-110): at dpcm_be_dai_trigger() on MultiMedia2 Capture [ 153.357875] MultiMedia2 Capture: ASoC error (-110): trigger FE cmd: 1 failed Revert the change for now, to fix the issue. This reverts commit cd0f5c6. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…org/pub/scm/linux/kernel/git/torvalds/linux.git tech/bsp/clk d8a14b9 30 tech/bsp/devfreq 5a26797 7 tech/bsp/soc-infra ff6ff7b 22 tech/bsp/pinctrl 79149ef 1 tech/bsp/remoteproc cbd11fb 10 tech/bus/peripherals fedd8c6 6 tech/bus/pci/all ebd808f 4 tech/bus/pci/phy 1f1f4b6 7 tech/bus/usb/dwc 9dd47ad 3 tech/bus/usb/phy c3aa7d5 35 tech/debug/hwtracing d9accac 22 tech/pmic/misc 6fb618c 8 tech/mem/iommu 44df12a 8 tech/mm/audio/all 88b8f29 8 tech/mm/camss c394dfb 32 tech/mm/drm 1d1d827 64 tech/mm/fastrpc e014e35 11 tech/mm/video 590953d 36 tech/mm/gpu 0b8d9f4 7 tech/net/ath 638841e 16 tech/pm/power bb88701 13 tech/pm/thermal d36b3ee 7 tech/security/crypto c36112e 14 tech/security/ice beabac0 9 tech/storage/all d86d915 4 tech/all/dt/qcs6490 db0d97d 20 tech/all/dt/qcs9100 166356c 88 tech/all/dt/qcs8300 cd0f5c6 22 tech/all/dt/qcs615 9a58c35 9 tech/all/dt/agatti c828f10 1 tech/all/dt/hamoa fa16fdb 36 tech/all/dt/glymur aba48bf 39 tech/all/dt/kaanapali c637991 19 tech/all/dt/pakala 960924d 13 tech/all/config 044539b 69 tech/overlay/dt 6a1064f 77 tech/all/workaround 2a67b15 26 tech/mproc/all 104969c 2 tech/noup/debug/all cbdd4bb 26 tech/hwe/unoq a2d85fe 4 early/hwe/shikra/drivers 46a583d 161 early/hwe/shikra/dt e6da759 122
On Glymur, there is an issue while working with the FP sensor connected to USB Hs only controller. The issue is as follows: 1) During boot, the usb controller initialises fine, but an error stating that the descriptor read from FP sensor failed and hence the controller is in an unknown state with failed enumeration of FP sensor. 2) At this point, the problem may be resource voting, but if unbind and rebind is done on the controller, enumeration is fine. All resources were thorughly checked and also schematic was checked to ensure that no GPIOs (if any) are left un-initialised. But resources seem to be fine. 3) When in this state, if we try to enter system suspend, GDSC too gets off, and also on resume we see that usb controller goes dead. And further attempts to enter suspend are gated by this dead controller. 4) If we re-bind controller on boot and then let enumration be successful, and then enter suspend, we see a SMMU crash on resume. On upstream code however, enumeration is fine on every reboot. This suspend-resume behavior is gating XO SD and hence disable it on CRD. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Pratham Pratap <pratham.pratap@oss.qualcomm.com>
…ng system resume On Glymur, display NoC errors are observed during system resume when MDSS register accesses occur before the MMCX/Display NoC path has scaled back to a voltage level sufficient for the required bandwidth. Keep the display clock controller's power-domain requirement at the turbo operating point as a temporary workaround to ensure the interconnect remains at a stable performance level during the resume sequence and avoid NoC errors triggered by early MDSS register access. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Enabling QSEECOM on Glymur CRD as below parameter is added in cmdline After the QSEECOM driver is enabled, the LoaderTpm2ActivePcrBanks UEFI variable is visible to userspace on Glymur platforms. This makes systemd wait for /dev/tpm0 during boot, but the secure TPM device is not yet enabled on Glymur. The missing TPM device adds a 90-second boot delay. Set `systemd.tpm2_wait=false` on the command line so systemd does not wait for a TPM device that is not currently available. This is a temporary change and is expected to be reverted by the end of September 2026, once the secure TPM is fully enabled on Glymur. This reverts commit e1374ed. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Add support for the contiguous hint (CONT) bit in ARM LPAE page tables.
When a set of consecutive PTEs map a naturally-aligned contiguous block
of memory, the CONT bit can be set on all entries in the group to allow
the hardware to combine them into a single TLB entry, improving TLB
utilization.
The contiguous hint sizes per granule are:
Page Size | CONT PTE | Block | CONT Block | L1 Block | CONT L1
----------+----------+---------+------------+----------+---------
4K | 64K | 2M | 32M | 1G | 16G
16K | 2M | 32M | 1G | |
64K | 2M | 512M | 16G | |
Contiguous hint sizes are advertised in pgsize_bitmap so that IOMMU API
users can align allocations to these sizes and benefit from the TLB
optimization automatically.
Partial unmaps of a contiguous group are rejected, ensuring the full
group is always invalidated as a unit. The
IO_PGTABLE_QUIRK_ARM_NO_CONT_HINT quirk allows SMMU drivers to disable
contiguous hint support at runtime for hardware with
implementation-specific errata.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Co-developed-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
Signed-off-by: Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
Signed-off-by: Prakash Gupta <prakash.gupta@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260722-iommu_contig_hint-v3-1-10923a683441@oss.qualcomm.com/
…nule issue Qualcomm SMMU-500 has an issue with TLBIVA/TLBIVAL where only the base-page-size entry at the base IOVA is invalidated, leaving stale TLB entries for the rest of the range. This causes use-after-free: after dma_free_coherent() unmaps a large buffer, the device can still access freed physical memory through stale TLB entries. On FastRPC workloads this manifests as ADSP crashes when the ELF loader writes to a freed PA that has been reallocated. Force the TLB invalidation step granule to the minimum page size for all Qualcomm SMMU-500 domains, ensuring each page in the range is individually invalidated. The minimum page size from pgsize_bitmap is used rather than hardcoded 4K to correctly handle 16K and 64K granule configurations. This increases the number of TLB invalidation operations for large ranges, but correctness takes precedence. Signed-off-by: Prakash Gupta <prakash.gupta@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
…omain When the remoteproc has an IOMMU (kernel running at EL2 without a separate hypervisor), memory carveouts must be explicitly mapped into the remoteproc's IOMMU domain so the DSP can access them. Without this mapping the DSP triggers an SMMU translation fault when accessing the remote heap carveout used for audio PD static process creation. Add has_iommu to fastrpc_channel_ctx, set from the "iommus" property of the remoteproc DT node. When set, map the ADSP remote heap carveout into the remoteproc's IOMMU domain using an identity mapping (IOVA == PA) via iommu_map(), and skip qcom_scm_assign_mem() which is only needed when a separate hypervisor manages inter-VM memory access control. Introduce fastrpc_remote_heap_map() and fastrpc_remote_heap_unmap() helpers to encapsulate the IOMMU domain lookup and map/unmap. Link: https://lore.kernel.org/all/20260618-audio_fix_clean_v3-v1-1-ec1ee66fe455@oss.qualcomm.com/ Signed-off-by: Anandu Krishnan E <anandu.e@oss.qualcomm.com>
…ling support The Qualcomm Crypto Engine (QCE) driver currently lacks support for runtime power management (PM) and interconnect bandwidth control. As a result, the hardware remains fully powered and clocks stay enabled even when the device is idle. Additionally, static interconnect bandwidth votes are held indefinitely, preventing the system from reclaiming unused bandwidth. Address this by enabling runtime PM and dynamic interconnect bandwidth scaling to allow the system to suspend the device when idle and scale interconnect usage based on actual demand. Improve overall system efficiency by reducing power usage and optimizing interconnect resource allocation. Signed-off-by: Udit Tiwari <udit.tiwari@oss.qualcomm.com> Tested-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260517105233.807935-1-udit.tiwari@oss.qualcomm.com
Enable CONFIG_HOTPLUG_PCI_PCIE to support native PCIe hotplug controllers on arm64 platforms. Link: https://lore.kernel.org/r/20260728-hotplug_pci-v1-1-d1f38cfb9122@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…latforms Commit eb3b5bf ("PCI: Whitelist native hotplug ports for runtime D3"), prevented native Hotplug capable Root Ports from entering D3 citing issues on old Intel SkyLake Xeon-SP platform. But there is no reason to restrict D3 for native Hotplug capable Root Ports on DT platforms. We recently enabled D3 on non-Hotplug capable Root Ports on non-x86 platforms (specifically for DT platforms) in commit a5fb3ff ("PCI: Allow PCI bridges to go to D3Hot on all non-x86"). So do the same for native Hotplug capable Root Ports as well. To honor the above platform_pci_bridge_d3() check, allow passing this check only for DT platforms, unlike a5fb3ff, which used !CONFIG_X86 check. Link: https://lore.kernel.org/all/20260729071514.859778-1-manivannan.sadhasivam@oss.qualcomm.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
…tions Enable the required crypto core options so dependent features like dmverity can select and use them. Signed-off-by: Sasi Kumar Maddineni <sasikuma@qti.qualcomm.com>
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
2 similar comments
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
Salendarsingh Gaud (sgaud-quic)
force-pushed
the
qcom-next
branch
from
August 12, 2026 05:18
8d5dbc1 to
49dbe0d
Compare
qcomlnxci
force-pushed
the
qcom-next
branch
2 times, most recently
from
August 18, 2026 11:08
21f58ca to
4020a6e
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
20 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Enable the required crypto core options so dependent features like dmverity can select and use them.
Fixes: https://github.com/qualcomm-linux/meta-qcom-distro/issues/377