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drivers: qcom: add GENI SPI driver and enable spi config #33

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Merged
Sumit Garg (b49020) merged 3 commits into from
Sep 22, 2026
Merged

drivers: qcom: add GENI SPI driver and enable spi config #33

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09c943b
drivers: qcom: add GENI SPI driver
Sep 21, 2026
d6a79fc
drivers: qcom: spi: add lemans SPI config
Sep 21, 2026
0d613f1
drivers: qcom: spi: add loopback SPI test
Sep 21, 2026
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1 change: 1 addition & 0 deletions core/arch/arm/plat-qcom/hoya/lemans/target.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@ CFG_DRIVERS_QCOM_CLK ?= y
CFG_QCOM_TLMM ?= y

CFG_QCOM_DIAG_LOG ?= $(CFG_TEE_CORE_DEBUG)
CFG_QCOM_GENI_SPI ?= y

ifneq ($(CFG_INSECURE),y)
CFG_QCOM_QFPROM_FUSEPROV ?= y
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220 changes: 220 additions & 0 deletions core/drivers/spi/qcom/platform/lemans/qcom_geni_spi_config.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,220 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

#include <drivers/qcom/tlmm/tlmm.h>
#include <drivers/qcom_geni_spi.h>
#include <mm/core_mmu.h>
#include <util.h>

static const uint8_t spi_qup_fw[] =
{
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};

#define QUP2_COMMON_BASE UL(0x008C0000)
register_phys_mem_pgdir(MEM_AREA_IO_SEC, QUP2_COMMON_BASE,
QUP_SPI_COMMON_REG_SIZE);

static const char *common_clocks_qup2[] = {
"gcc_qupv3_wrap2_core_2x_clk",
"gcc_qupv3_wrap2_core_clk",
"gcc_qupv3_wrap_2_s_ahb_clk",
"gcc_qupv3_wrap_2_m_ahb_clk",
NULL,
};

/*
* Lemans has a single SPI consumer: the dTPM on QUP2 SE2. Only that SE is
* configured; other platforms' SPI SEs belong to their own platform config.
*/
#define QUP2_SE2_SPI_ID 15
#define QUP2_SE2_SPI_BASE UL(0x00888000)
#define QUP2_SE2_SPI_IRQ 616

register_phys_mem_pgdir(MEM_AREA_IO_SEC, QUP2_SE2_SPI_BASE, QUP_SPI_REG_SIZE);

#define QUP2_SE2_SPI_MISO_PIN 86
#define QUP2_SE2_SPI_MOSI_PIN 87
#define QUP2_SE2_SPI_CLK_PIN 88
#define QUP2_SE2_SPI_CS_PIN 89

static const unsigned int qup2_se2_spi_g0_pins[] = {
QUP2_SE2_SPI_MISO_PIN,
QUP2_SE2_SPI_MOSI_PIN,
QUP2_SE2_SPI_CS_PIN,
};
static const unsigned int qup2_se2_spi_g1_pins[] = {
QUP2_SE2_SPI_CLK_PIN,
};

static const struct tlmm_pin_group qup2_se2_spi_pin_groups[] = {
{
.pins = qup2_se2_spi_g0_pins,
.pin_count = ARRAY_SIZE(qup2_se2_spi_g0_pins),
.func = 1,
.pull = TLMM_PULL_DOWN,
.drive_ma = 6,
.strong_pull = false,
},
{
.pins = qup2_se2_spi_g1_pins,
.pin_count = ARRAY_SIZE(qup2_se2_spi_g1_pins),
.func = 1,
.pull = TLMM_PULL_NONE,
.drive_ma = 6,
.strong_pull = false,
},
};

const struct qup_spi_platform_cfg qup_spi_config[] = {
{
.id = QUP2_SE2_SPI_ID,
.base = QUP2_SE2_SPI_BASE,
.common_base = QUP2_COMMON_BASE,
.itr_num = QUP2_SE2_SPI_IRQ,
.clk_hz = 19200000,
.se_clock_name = "gcc_qupv3_wrap2_s2_clk",
.common_clocks_name = common_clocks_qup2,
.pin_groups = qup2_se2_spi_pin_groups,
.pin_group_count = ARRAY_SIZE(qup2_se2_spi_pin_groups),
.fw_image = spi_qup_fw,
.fw_image_size = sizeof(spi_qup_fw),
},
};
Comment thread
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const size_t qup_spi_config_count = ARRAY_SIZE(qup_spi_config);
1 change: 1 addition & 0 deletions core/drivers/spi/qcom/platform/lemans/sub.mk
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srcs-$(CFG_QCOM_GENI_SPI) += qcom_geni_spi_config.c
1 change: 1 addition & 0 deletions core/drivers/spi/qcom/platform/sub.mk
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subdirs-y += $(PLATFORM_FLAVOR)
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