plat-qcom nord pil framework enablement

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@@ -146,6 +146,11 @@ S:	Maintained
 F:	core/drivers/qcom/cmd_db/
 F:	core/include/drivers/qcom/cmd_db/
 
+Core Drivers QCOM HWKM
+R:	Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> [@qc-azarrabi]
+S:	Maintained
+F:	core/drivers/crypto/qcom/
+
 Core Drivers QCOM QFPROM
 R:	Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> [@zelvam95]
 R:	Kishore Batta <kishore.batta@oss.qualcomm.com> [@kishorebatta-ossqcom]

core/arch/arm/plat-qcom/bobcat/ipq52xx/target.mk

@@ -6,3 +6,10 @@ CFG_QCOM_DIAG_LOG ?= $(CFG_TEE_CORE_DEBUG)
 CFG_TZDRAM_START ?= 0x87D80000
 CFG_TZDRAM_SIZE ?= 0x280000
 CFG_TEE_RAM_VA_SIZE ?= 0x280000
+
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
+
+CFG_HWRNG_PTA ?= y
+CFG_HWRNG_QUALITY ?= 1024
+CFG_HWRNG_RATE ?= 0

core/arch/arm/plat-qcom/bobcat/ipq52xx/target_config.h

@@ -20,4 +20,9 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x18000)
 
+#define QCOM_RNG_REG_BASE		UL(0x4C5000)
+
+#define QCOM_WDT_TMR_BASE		UL(0x0B117000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x23)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/ipq96xx/target_config.h

@@ -19,4 +19,7 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x20000)
 
+#define QCOM_WDT_TMR_BASE		UL(0x0F411000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x36)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/qcom-arch.mk

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+CFG_QCOM_SEC_WDOG ?= y
+
+# XPU protection for TZDRAM and the OP-TEE DIAG log buffer
+CFG_QCOM_XPUV4 ?= y

core/arch/arm/plat-qcom/hoya/arch_config.h

@@ -11,7 +11,7 @@
 #define GICR_BASE			UL(0x17a60000)
 
 #define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
-#define SEC_PRNG_REG_BASE		UL(0x010D1000)
+#define QCOM_RNG_REG_BASE		UL(0x010D1000)
 
 #define AOP_MSG_RAM_BASE		UL(0x0C300000)
 #define AOP_MSG_RAM_SIZE		UL(0x00100000)
@@ -25,6 +25,9 @@
 #define TCSR_MUTEX_BASE			UL(0x01F40000)
 #define TCSR_MUTEX_SIZE			UL(0x40000)
 
+#define HWKM_MASTER_BASE		UL(0x010c0000)
+#define HWKM_MASTER_SIZE		UL(0x00020000)
+
 #define IMEM_DIAG_OFFSET		UL(0x720)
 #define DIAG_SIZE			UL(0x3000)
 #define DIAG_BASE			(IMEM_BASE + IMEM_SIZE - DIAG_SIZE)

core/arch/arm/plat-qcom/hoya/lemans/target.mk

@@ -12,3 +12,15 @@ $(call force,CFG_QCOM_CMD_DB,y)
 $(call force,CFG_QCOM_RPMH_CLIENT,y)
 $(call force,CFG_QCOM_QFPROM,y)
 endif
+
+CFG_QCOM_PAS_PTA ?= y
+
+ifeq ($(CFG_QCOM_PAS_PTA),y)
+CFG_RESERVED_VASPACE_SIZE ?= (256 * 1024 * 1024)
+CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+
+CFG_QCOM_PAS_AUTH ?= y
+
+CFG_PAS_MD_SLOTS ?= 8
+endif
+CFG_QCOM_HWKM ?= y

core/arch/arm/plat-qcom/hoya/lemans/target_config.h

@@ -30,4 +30,68 @@
 #define IMEM_BASE			UL(0x14680000)
 #define IMEM_SIZE			UL(0x32000)
 
+#define TURING_0_BASE			UL(0x24000000)
+#define TURING_0_SIZE			UL(0x03000000)
+
+#define TURING_1_BASE			UL(0x28000000)
+#define TURING_1_SIZE			UL(0x03000000)
+
+/*
+ * GP-DSP0 / GP-DSP1 (TURINGGDSP / TURINGGDSP1) subsystems. The window covers
+ * every GP-DSP sub-block the PTA and clock driver touch (GDSP_CC 0x808000, PUB
+ * 0xc00000, PLL 0xc40000, CORE_CC 0xc48000).
+ */
+#define TURING_GDSP_0_BASE		UL(0x20000000)
+#define TURING_GDSP_0_SIZE		UL(0x01000000)
+
+#define TURING_GDSP_1_BASE		UL(0x21000000)
+#define TURING_GDSP_1_SIZE		UL(0x01000000)
+
+/*
+ * LPASS / ADSP (QDSP6 v68/v69) subsystem window, covering every sub-block the
+ * PTA and clock driver touch (PUB, PLL, CORE_CC, AON_CC, MCC, TOP_CC).
+ */
+#define LPASS_BASE			UL(0x02c00000)
+#define LPASS_SIZE			ULL(0x01080000)
+
+/*
+ * IRIS video-codec subsystem. The window covers the VCODEC_IRIS_WRAPPER_TOP
+ * (IRIS+0xb0000) and WRAPPER_TZ (IRIS+0xc0000) blocks the bring-up path
+ * touches.
+ */
+#define IRIS_BASE			UL(0x0aa00000)
+#define IRIS_SIZE			ULL(0x00200000)
+
+/* CDSP0 content-protection shared channel (secure DDR); no CDSP1 equivalent. */
+#define CDSP_SECCHANNEL_BASE		UL(0xdb1dc000)
+#define CDSP_SECCHANNEL_SIZE		UL(0x2000)
+
+/*
+ * Global register blocks for the Turing/NSP reset sequence, under AOSS_BASE
+ * (0x0b000000). TCSR_MUTEX_BASE/SIZE is already defined in arch_config.h.
+ */
+#define AOSS_CC_BASE			UL(0x0c2a8000)
+#define AOSS_CC_SIZE			UL(0x00050000)
+
+#define RPMH_PDC_GLOBAL_BASE		UL(0x0b5e0000)
+#define RPMH_PDC_GLOBAL_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_COMPUTE_BASE		UL(0x0b2c0000)
+#define RPMH_PDC_COMPUTE_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_NSP_BASE		UL(0x0b2f0000)
+#define RPMH_PDC_NSP_SIZE		UL(0x00002000)
+
+/*
+ * RPMH PDC blocks for the GP-DSP subsystem reset sequence. These live under
+ * AOSS_BASE (0x0b000000), at offsets 0x240000 / 0x2d0000.
+ */
+#define RPMH_PDC_GPDSP0_BASE		UL(0x0b240000)
+#define RPMH_PDC_GPDSP0_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_GPDSP1_BASE		UL(0x0b2d0000)
+#define RPMH_PDC_GPDSP1_SIZE		UL(0x00002000)
+
+#define TITAN_SS_BASE			UL(0x0ac00000)
+#define TITAN_SS_SIZE			UL(0x00200000)
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/qcom-arch.mk

@@ -6,7 +6,8 @@ $(call force,CFG_TEE_CORE_NB_CORE,8)
 $(call force,CFG_QCOM_RAMBLUR_PIMEM_V3,y)
 CFG_QCOM_RAMBLUR_TA_WINDOW_ID ?= 2
 
-$(call force,CFG_QCOM_PRNG,y)
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
 $(call force,CFG_ARM_GICV3,y)
 
 CFG_TZDRAM_START ?= 0x1c300000

core/arch/arm/plat-qcom/wildcat/arch_config.h

@@ -9,4 +9,19 @@
 #define GICD_BASE			UL(0x17000000)
 #define GICR_BASE			UL(0x17080000)
 
+#define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
+#define SEC_PRNG_REG_BASE		UL(0x010D1000)
+
+#define AOP_MSG_RAM_BASE		UL(0x0C300000)
+#define AOP_MSG_RAM_SIZE		UL(0x00100000)
+
+#define RPMH_BASE_ADDR			UL(0x18200000)
+#define RPMH_RSC_SIZE			UL(0x40000)
+
+#define SECURITY_CONTROL_BASE		UL(0x00780000)
+#define SECURITY_CONTROL_SIZE		UL(0x10000)
+
+#define TCSR_MUTEX_BASE			UL(0x01F40000)
+#define TCSR_MUTEX_SIZE			UL(0xC0000)
+
 #endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/wildcat/nord/target.mk

@@ -3,3 +3,25 @@
 # Threads are expensive in OP-TEE, so they don't have
 # to be same as number of cores.
 $(call force,CFG_TEE_CORE_NB_CORE,18)
+
+CFG_DRIVERS_CLK ?= y
+CFG_DRIVERS_QCOM_CLK ?= y
+
+ifneq ($(CFG_INSECURE),y)
+CFG_QCOM_QFPROM_FUSEPROV ?= y
+endif
+
+ifeq ($(CFG_QCOM_QFPROM_FUSEPROV),y)
+$(call force,CFG_QCOM_CMD_DB,y)
+$(call force,CFG_QCOM_RPMH_CLIENT,y)
+$(call force,CFG_QCOM_QFPROM,y)
+endif
+
+CFG_QCOM_PAS_PTA ?= y
+
+ifeq ($(CFG_QCOM_PAS_PTA),y)
+CFG_QCOM_PAS_AUTH ?= y
+CFG_PAS_MD_SLOTS ?= 8
+CFG_RESERVED_VASPACE_SIZE ?= (64 * 1024 * 1024)
+CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+endif

core/arch/arm/plat-qcom/wildcat/nord/target_config.h

@@ -6,11 +6,77 @@
 #ifndef TARGET_CONFIG_H
 #define TARGET_CONFIG_H
 
-#define GENI_UART_REG_BASE		UL(0x884000)
+#define GCC_BASE			UL(0x110000)
+#define GCC_SIZE			UL(0x100000)
+
+#define AOP_CMD_DB_BASE			UL(0x90860000)
+#define AOP_CMD_DB_SIZE			UL(0x00020000)
+
+#define CFG_SEC_ELF_DDR_ADDR		UL(0x908FF000)
+#define CFG_SEC_ELF_DDR_SIZE		UL(0x1000)
 
 #define DRAM0_BASE			UL(0x80000000)
 #define DRAM0_SIZE			UL(0x380000000)
 #define DRAM1_BASE			ULL(0x800000000)
 #define DRAM1_SIZE			ULL(0x800000000)
 
+#define GENI_UART_REG_BASE		UL(0x884000)
+
+#define IMEM_BASE			UL(0x14680000)
+#define IMEM_SIZE			UL(0x32000)
+
+#define CDSP_0_BASE			UL(0x1f0c8000)
+#define CDSP_0_SIZE			UL(0x00280000)
+
+#define CDSP_1_BASE			UL(0x1f4c8000)
+#define CDSP_1_SIZE			UL(0x00280000)
+
+#define CDSP_2_BASE			UL(0x1f8c8000)
+#define CDSP_2_SIZE			UL(0x00280000)
+
+#define CDSP_3_BASE			UL(0x1fcc8000)
+#define CDSP_3_SIZE			UL(0x00280000)
+
+#define HPASS_0_BASE			UL(0x04c00000)
+#define HPASS_0_SIZE			UL(0x00100000)
+
+#define HPASS_1_BASE			UL(0x06000000)
+#define HPASS_1_SIZE			UL(0x00100000)
+
+#define HPASS_2_BASE			UL(0x06100000)
+#define HPASS_2_SIZE			UL(0x00100000)
+
+#define HPASS_CC_BASE			UL(0x05508000)
+#define HPASS_CC_SIZE			UL(0x00020000)
+
+#define HPASS_TCM_BASE			UL(0x05700000)
+#define HPASS_TCM_SIZE			UL(0x00001000)
+
+#define HPASS_TCSR_BASE			UL(0x05580000)
+#define HPASS_TCSR_SIZE			UL(0x00020000)
+
+#define SE_GCC_BASE			UL(0x08a10000)
+#define SE_GCC_SIZE			UL(0x00013000)
+
+#define SOCCP_CSR_BASE			UL(0x00d40000)
+#define SOCCP_CSR_SIZE			UL(0x00040000)
+
+#define QDSS_SOCCP_DMI_BASE		UL(0x11508000)
+#define QDSS_SOCCP_DMI_SIZE		UL(0x00001000)
+
+#define AOSS_CC_BASE			UL(0x0c2f0000)
+#define AOSS_CC_SIZE			UL(0x00010000)
+
+#define RPMH_PDC_GLOBAL_BASE		UL(0x0b5e6000)
+#define RPMH_PDC_GLOBAL_SIZE		UL(0x0000a000)
+
+#define FUSE_CONTROLLER_SW_RANGE4_BASE	UL(0x360d4000)
+#define FUSE_CONTROLLER_SW_RANGE4_SIZE	UL(0x00001000)
+
+/*
+ * IRIS video-codec subsystem.
+ */
+#define IRIS_BASE			UL(0x0aa00000)
+#define IRIS_SIZE			ULL(0x00200000)
+
 #endif /* TARGET_CONFIG_H */