drivers/qcom/rng: enable CSRNG on Nord and Shikra chipsets

.github/workflows/ci.yml

@@ -217,6 +217,8 @@ jobs:
               _make PLATFORM=qcom-ipq96xx
               _make PLATFORM=qcom-ipq52xx
               _make PLATFORM=qcom-nord
+              _make PLATFORM=qcom-cacao
+              _make PLATFORM=qcom-shikra
           - name: arm rockchip
             make_commands: |
               _make PLATFORM=rockchip-px30

MAINTAINERS

@@ -146,6 +146,11 @@ S:	Maintained
 F:	core/drivers/qcom/cmd_db/
 F:	core/include/drivers/qcom/cmd_db/
 
+Core Drivers QCOM HWKM
+R:	Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> [@qc-azarrabi]
+S:	Maintained
+F:	core/drivers/crypto/qcom/
+
 Core Drivers QCOM QFPROM
 R:	Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> [@zelvam95]
 R:	Kishore Batta <kishore.batta@oss.qualcomm.com> [@kishorebatta-ossqcom]

core/arch/arm/plat-qcom/bobcat/ipq52xx/target.mk

@@ -6,3 +6,10 @@ CFG_QCOM_DIAG_LOG ?= $(CFG_TEE_CORE_DEBUG)
 CFG_TZDRAM_START ?= 0x87D80000
 CFG_TZDRAM_SIZE ?= 0x280000
 CFG_TEE_RAM_VA_SIZE ?= 0x280000
+
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
+
+CFG_HWRNG_PTA ?= y
+CFG_HWRNG_QUALITY ?= 1024
+CFG_HWRNG_RATE ?= 0

core/arch/arm/plat-qcom/bobcat/ipq52xx/target_config.h

@@ -20,4 +20,9 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x18000)
 
+#define QCOM_RNG_REG_BASE		UL(0x4C5000)
+
+#define QCOM_WDT_TMR_BASE		UL(0x0B117000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x23)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/ipq96xx/target_config.h

@@ -19,4 +19,7 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x20000)
 
+#define QCOM_WDT_TMR_BASE		UL(0x0F411000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x36)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/qcom-arch.mk

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+CFG_QCOM_SEC_WDOG ?= y
+
+# XPU protection for TZDRAM and the OP-TEE DIAG log buffer
+CFG_QCOM_XPUV4 ?= y

core/arch/arm/plat-qcom/bruin/arch_config.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef ARCH_CONFIG_H
+#define ARCH_CONFIG_H
+
+#define GICD_BASE			UL(0x0f200000)
+#define GICR_BASE			UL(0x0f260000)
+
+#endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/bruin/qcom-arch.mk

@@ -0,0 +1,11 @@
+# BRUIN architecture configuration
+
+include core/arch/arm/cpu/cortex-armv8-0.mk
+$(call force,CFG_TEE_CORE_NB_CORE,4)
+$(call force,CFG_ARM_GICV3,y)
+
+CFG_TZDRAM_START ?= 0xa1400000
+CFG_TEE_RAM_VA_SIZE ?= 0x400000
+CFG_TA_RAM_VA_SIZE ?= 0x2100000
+CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE)
+CFG_NUM_THREADS ?= 4

core/arch/arm/plat-qcom/bruin/shikra/target.mk

@@ -0,0 +1,4 @@
+# Enable the Qualcomm CSRNG hardware RNG driver.
+# Shikra uses the legacy PRNG block via HWKM MMIO.
+# Register offsets and base address are defined in target_config.h.
+$(call force,CFG_QCOM_CSRNG,y)

core/arch/arm/plat-qcom/bruin/shikra/target_config.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x80000000)
+
+#define GENI_UART_REG_BASE		UL(0x04a80000)
+
+#define IMEM_BASE			UL(0x0c100000)
+#define IMEM_SIZE			UL(0x00020000)
+
+#define QCOM_RNG_REG_BASE			UL(0x04450000)
+#define QCOM_RNG_REG_SIZE			UL(0x00020000)
+#define QCOM_RNG_DATA_OUT			0x1000
+#define QCOM_RNG_STATUS				0x1004
+
+#endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bruin/sub.mk

@@ -0,0 +1 @@
+# Placeholder for Qcom architecture specific makefile

core/arch/arm/plat-qcom/conf.mk

@@ -31,14 +31,17 @@ supported-ta-targets ?= ta_arm64
 # Architecture family mapping
 HOYA_ARCH_CHIPSETS := kodiak lemans
 BOBCAT_ARCH_CHIPSETS := ipq96xx ipq52xx
-WILDCAT_ARCH_CHIPSETS := nord
+WILDCAT_ARCH_CHIPSETS := nord cacao
+BRUIN_ARCH_CHIPSETS := shikra
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(HOYA_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := hoya
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(BOBCAT_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := bobcat
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(WILDCAT_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := wildcat
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(BRUIN_ARCH_CHIPSETS)))
+QCOM_ARCH_FAMILY := bruin
 else
 $(error Unsupported PLATFORM_FLAVOR: $(PLATFORM_FLAVOR))
 endif

core/arch/arm/plat-qcom/hoya/arch_config.h

@@ -11,7 +11,6 @@
 #define GICR_BASE			UL(0x17a60000)
 
 #define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
-#define SEC_PRNG_REG_BASE		UL(0x010D1000)
 
 #define AOP_MSG_RAM_BASE		UL(0x0C300000)
 #define AOP_MSG_RAM_SIZE		UL(0x00100000)
@@ -25,6 +24,9 @@
 #define TCSR_MUTEX_BASE			UL(0x01F40000)
 #define TCSR_MUTEX_SIZE			UL(0x40000)
 
+#define HWKM_MASTER_BASE		UL(0x010c0000)
+#define HWKM_MASTER_SIZE		UL(0x00020000)
+
 #define IMEM_DIAG_OFFSET		UL(0x720)
 #define DIAG_SIZE			UL(0x3000)
 #define DIAG_BASE			(IMEM_BASE + IMEM_SIZE - DIAG_SIZE)

core/arch/arm/plat-qcom/hoya/kodiak/target_config.h

@@ -39,4 +39,10 @@
 #define IRIS_BASE			UL(0x0aa00000)
 #define IRIS_SIZE			ULL(0x00200000)
 
+/* Configuration Registers for RNG */
+#define QCOM_RNG_REG_BASE      UL(0x010D0000)
+#define QCOM_RNG_REG_SIZE      UL(0x00020000)
+#define QCOM_RNG_DATA_OUT      0x1000
+#define QCOM_RNG_STATUS        0x1004
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/lemans/target.mk

@@ -12,3 +12,14 @@ $(call force,CFG_QCOM_CMD_DB,y)
 $(call force,CFG_QCOM_RPMH_CLIENT,y)
 $(call force,CFG_QCOM_QFPROM,y)
 endif
+
+CFG_QCOM_PAS_PTA ?= y
+
+ifeq ($(CFG_QCOM_PAS_PTA),y)
+# PAS subsystems map their controller windows at runtime from the reserved VA
+# pool (never released). The six DSP windows total ~146.5 MB; the 60 MB default
+# fits only one, so reserve 256 MB with headroom.
+CFG_RESERVED_VASPACE_SIZE ?= (256 * 1024 * 1024)
+CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+endif
+CFG_QCOM_HWKM ?= y

core/arch/arm/plat-qcom/hoya/lemans/target_config.h

@@ -30,4 +30,74 @@
 #define IMEM_BASE			UL(0x14680000)
 #define IMEM_SIZE			UL(0x32000)
 
+#define TURING_0_BASE			UL(0x24000000)
+#define TURING_0_SIZE			UL(0x03000000)
+
+#define TURING_1_BASE			UL(0x28000000)
+#define TURING_1_SIZE			UL(0x03000000)
+
+/*
+ * GP-DSP0 / GP-DSP1 (TURINGGDSP / TURINGGDSP1) subsystems. The window covers
+ * every GP-DSP sub-block the PTA and clock driver touch (GDSP_CC 0x808000, PUB
+ * 0xc00000, PLL 0xc40000, CORE_CC 0xc48000).
+ */
+#define TURING_GDSP_0_BASE		UL(0x20000000)
+#define TURING_GDSP_0_SIZE		UL(0x01000000)
+
+#define TURING_GDSP_1_BASE		UL(0x21000000)
+#define TURING_GDSP_1_SIZE		UL(0x01000000)
+
+/*
+ * LPASS / ADSP (QDSP6 v68/v69) subsystem window, covering every sub-block the
+ * PTA and clock driver touch (PUB, PLL, CORE_CC, AON_CC, MCC, TOP_CC).
+ */
+#define LPASS_BASE			UL(0x02c00000)
+#define LPASS_SIZE			ULL(0x01080000)
+
+/*
+ * IRIS video-codec subsystem. The window covers the VCODEC_IRIS_WRAPPER_TOP
+ * (IRIS+0xb0000) and WRAPPER_TZ (IRIS+0xc0000) blocks the bring-up path
+ * touches.
+ */
+#define IRIS_BASE			UL(0x0aa00000)
+#define IRIS_SIZE			ULL(0x00200000)
+
+/* CDSP0 content-protection shared channel (secure DDR); no CDSP1 equivalent. */
+#define CDSP_SECCHANNEL_BASE		UL(0xdb1dc000)
+#define CDSP_SECCHANNEL_SIZE		UL(0x2000)
+
+/*
+ * Global register blocks for the Turing/NSP reset sequence, under AOSS_BASE
+ * (0x0b000000). TCSR_MUTEX_BASE/SIZE is already defined in arch_config.h.
+ */
+#define AOSS_CC_BASE			UL(0x0c2a8000)
+#define AOSS_CC_SIZE			UL(0x00050000)
+
+#define RPMH_PDC_GLOBAL_BASE		UL(0x0b5e0000)
+#define RPMH_PDC_GLOBAL_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_COMPUTE_BASE		UL(0x0b2c0000)
+#define RPMH_PDC_COMPUTE_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_NSP_BASE		UL(0x0b2f0000)
+#define RPMH_PDC_NSP_SIZE		UL(0x00002000)
+
+/*
+ * RPMH PDC blocks for the GP-DSP subsystem reset sequence. These live under
+ * AOSS_BASE (0x0b000000), at offsets 0x240000 / 0x2d0000.
+ */
+#define RPMH_PDC_GPDSP0_BASE		UL(0x0b240000)
+#define RPMH_PDC_GPDSP0_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_GPDSP1_BASE		UL(0x0b2d0000)
+#define RPMH_PDC_GPDSP1_SIZE		UL(0x00002000)
+
+/* Configuration Registers for RNG */
+#define QCOM_RNG_REG_BASE      UL(0x010D0000)
+#define QCOM_RNG_REG_SIZE      UL(0x00020000)
+#define QCOM_RNG_DATA_OUT      0x1000
+#define QCOM_RNG_STATUS        0x1004
+
+#define TITAN_SS_BASE			UL(0x0ac00000)
+#define TITAN_SS_SIZE			UL(0x00200000)
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/qcom-arch.mk

@@ -6,7 +6,8 @@ $(call force,CFG_TEE_CORE_NB_CORE,8)
 $(call force,CFG_QCOM_RAMBLUR_PIMEM_V3,y)
 CFG_QCOM_RAMBLUR_TA_WINDOW_ID ?= 2
 
-$(call force,CFG_QCOM_PRNG,y)
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
 $(call force,CFG_ARM_GICV3,y)
 
 CFG_TZDRAM_START ?= 0x1c300000

core/arch/arm/plat-qcom/wildcat/arch_config.h

@@ -6,7 +6,4 @@
 #ifndef ARCH_CONFIG_H
 #define ARCH_CONFIG_H
 
-#define GICD_BASE			UL(0x17000000)
-#define GICR_BASE			UL(0x17080000)
-
 #endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/wildcat/cacao/target.mk

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+# Qualcomm Cacao platform configuration.
+
+$(call force,CFG_TEE_CORE_NB_CORE,8)
+
+# DARE-TZ secure memory regions. DARE is an in-line memory encryption
+# IP on Wildcat; it is set up by the TME root-of-trust before OP-TEE
+# runs, so no specific OP-TEE driver is needed.
+CFG_TZDRAM_START ?= 0x80fcd000
+CFG_TEE_RAM_VA_SIZE ?= 0x147000
+CFG_TA_RAM_VA_SIZE ?= 0x300000

core/arch/arm/plat-qcom/wildcat/cacao/target_config.h

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#define TCSR_BOOT_MISC_DETECT		UL(0x1FD3000)
+
+#define IMEM_BASE			UL(0x14680000)
+#define IMEM_SIZE			UL(0x19000)
+
+#define GICD_BASE			UL(0x17200000)
+#define GICR_BASE			UL(0x17260000)
+
+#define GCC_BASE			UL(0x00100000)
+#define GCC_SIZE			UL(0x001f0000)
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x10000000)
+
+#define GENI_UART_REG_BASE		UL(0xa94000)
+
+#endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/wildcat/nord/target.mk

@@ -3,3 +3,15 @@
 # Threads are expensive in OP-TEE, so they don't have
 # to be same as number of cores.
 $(call force,CFG_TEE_CORE_NB_CORE,18)
+
+# DARE-TZ secure memory regions. DARE is another in-line
+# memory encryption IP similar to pIMEM but on wildcat arch
+# it is setup by TME root-of-trust, no specific driver needed
+# in OP-TEE for that.
+CFG_TZDRAM_START ?= 0xBC280000
+CFG_TEE_RAM_VA_SIZE ?= 0x00200000
+CFG_TA_RAM_VA_SIZE ?= 0x07B80000
+
+# Enable the Qualcomm CSRNG hardware RNG driver.
+# Register offsets and base address are defined in target_config.h.
+$(call force,CFG_QCOM_CSRNG,y)

core/arch/arm/plat-qcom/wildcat/nord/target_config.h

@@ -8,9 +8,17 @@
 
 #define GENI_UART_REG_BASE		UL(0x884000)
 
+#define GICD_BASE			UL(0x17000000)
+#define GICR_BASE			UL(0x17080000)
+
 #define DRAM0_BASE			UL(0x80000000)
 #define DRAM0_SIZE			UL(0x380000000)
 #define DRAM1_BASE			ULL(0x800000000)
 #define DRAM1_SIZE			ULL(0x800000000)
 
+#define QCOM_RNG_REG_BASE			UL(0x010C0000)
+#define QCOM_RNG_REG_SIZE			UL(0x2000)
+#define QCOM_RNG_DATA_OUT			0x1000
+#define QCOM_RNG_STATUS				0x1004
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/wildcat/qcom-arch.mk

@@ -1,15 +1,11 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
 # Wildcat architecture configuration
 
 include core/arch/arm/cpu/cortex-armv8-0.mk
 
 $(call force,CFG_ARM_GICV4,y)
 
-# DARE-TZ secure memory regions. DARE is another in-line
-# memory encryption IP similar to pIMEM but on wildcat arch
-# it is setup by TME root-of-trust, no specific driver needed
-# in OP-TEE for that.
-CFG_TZDRAM_START ?= 0xBC280000
-CFG_TEE_RAM_VA_SIZE ?= 0x00200000
-CFG_TA_RAM_VA_SIZE ?= 0x07B80000
 CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE)
 CFG_NUM_THREADS ?= 8