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drivers: qcom: rpmh: add nord support #65

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13 changes: 13 additions & 0 deletions core/arch/arm/plat-qcom/wildcat/nord/target.mk
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Expand Up @@ -11,3 +11,16 @@ $(call force,CFG_TEE_CORE_NB_CORE,18)
CFG_TZDRAM_START ?= 0xBC280000
CFG_TEE_RAM_VA_SIZE ?= 0x00200000
CFG_TA_RAM_VA_SIZE ?= 0x07B80000

ifneq ($(CFG_INSECURE),y)

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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QFPROM in OTPEE isn't applicable for Nord, you can make it default NO.
Or you can clean up this part completely from you pull request onus is on platform or client driver not us to update the same unless it's causing issues in rpmh/cmd-db driver enablement

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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Sure

CFG_QCOM_QFPROM_FUSEPROV ?= y
endif

ifeq ($(CFG_QCOM_QFPROM_FUSEPROV),y)

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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rpmh/cmd_db initialization shouldn't be dependent on qfprom, it should be independent cleanup top level check

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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Will update.

$(call force,CFG_QCOM_CMD_DB,y)
$(call force,CFG_QCOM_RPMH_CLIENT,y)
endif

ifneq ($(filter y,$(CFG_QCOM_QFPROM_FUSEPROV) $(CFG_QCOM_FUSE_PTA)),)

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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cleanup this part.

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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Sure

$(call force,CFG_QCOM_QFPROM,y)
endif
21 changes: 16 additions & 5 deletions core/arch/arm/plat-qcom/wildcat/nord/target_config.h
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Expand Up @@ -10,12 +10,23 @@

#define GICD_BASE UL(0x17000000)
#define GICR_BASE UL(0x17080000)
#define AOP_CMD_DB_BASE UL(0x87148000)

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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correct indent throughout the file

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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Okay


#define AOP_CMD_DB_SIZE UL(0x2000)

#define AOP_MSG_RAM_BASE UL(0x0C300000)
#define AOP_MSG_RAM_SIZE UL(0x00100000)
#define MSG_RAM_SECTION_SIZE UL(0x00001000)

#define RPMH_BASE_ADDR UL(0x18900000)
#define RPMH_RSC_SIZE UL(0x10000)


#define DRAM0_BASE UL(0x80000000)
#define DRAM0_SIZE UL(0x80000000)
#define DRAM1_BASE ULL(0x880000000)
#define DRAM1_SIZE ULL(0x780000000)
#define DRAM2_BASE ULL(0x8800000000)
#define DRAM2_SIZE ULL(0x3800000000)
#define DRAM0_SIZE UL(0x80000000)

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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these aren't expected to be used in rpmh/cmd-db drivers, restore this change.

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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It's just an indent issue, will fix.

#define DRAM1_BASE ULL(0x880000000)
#define DRAM1_SIZE ULL(0x780000000)
#define DRAM2_BASE ULL(0x8800000000)
#define DRAM2_SIZE ULL(0x3800000000)

#endif /* TARGET_CONFIG_H */
40 changes: 40 additions & 0 deletions core/drivers/qcom/rpmh/nord/rpmh_drv_config.c
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@@ -0,0 +1,40 @@
// SPDX-License-Identifier: BSD-2-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

#include <stddef.h>

#include "rpmh_drv_config.h"
#include "rpmh_target_config.h"

static const struct tcs_config tcs_config_tz = {
.amcs = RPMH_TCS_SLEEP - RPMH_TCS_AMC,
.sleep_start = RPMH_TCS_SLEEP,
.wake_start = RPMH_TCS_WAKE,
};

static const struct drv_config_data optee_config_data = {
.drvs_count = 1,
.init_clks_count = 0,

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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in parent driver these struct members may be used but they aren't expected to - review and change the design at right place.

@shvm-ap Shivam Sanjay (shvm-ap) Sep 17, 2026

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Are you suggesting to clean these up, and then use Macros instead?

.init_clks = NULL,
.sleep_clks_count = 0,
.sleep_clks = NULL,

.drvs = (struct drv_config[]) {
{
.drv_id = RSC_DRV_SECURE,
.hw_drv = RSC_DRV_SECURE,
.wake_set_latency = 0x7080, /* 1.5ms in 19.2MHz */
.tcs_offset = 0,
.tcs = RPMH_TCS_MAX,
.cmds = RPMH_MAX_CMDS_PER_TCS,
.modes_count = 1,
.modes = (const struct tcs_config *[]) {
&tcs_config_tz,
}
}
}
};

const struct drv_config_data *const g_drv_config_data = &optee_config_data;
57 changes: 57 additions & 0 deletions core/drivers/qcom/rpmh/nord/rpmh_hwio.h
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@@ -0,0 +1,57 @@
/* SPDX-License-Identifier: BSD-2-Clause */

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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same set of comments as
#55

/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

#ifndef __RPMH_HWIO_H__
#define __RPMH_HWIO_H__

#include <util.h>

#define DRV_STRIDE 0x10000
#define RSC_DRV_IRQ_ENABLE 0x0d00
#define RSC_DRV_IRQ_STATUS 0x0d04
#define RSC_DRV_IRQ_CLEAR 0x0d08

#define RSC_DRV_TCS_CONFIG 0x0C
#define TCS_BASE_OFFSET 0x0D20
#define TCS_STRIDE 0x2A0

#define TCS_CONTROL_OFFSET 0x04
#define TCS_STATUS_OFFSET 0x08
#define TCS_CMD_ENABLE_OFFSET 0x0C

#define TCS_PROFILING_STATUS_OFFSET 0x10

#define TCS_CMD_BASE_OFFSET 0x14
#define TCS_CMDn_MSGID_OFFSET 0x00
#define TCS_CMDn_ADDR_OFFSET 0x04
#define TCS_CMDn_DATA_OFFSET 0x08
#define TCS_CMD_STRIDE 0x18

#define TCS_CONTROL_AMC_MODE_TRIGGER BIT(24)
#define TCS_CONTROL_AMC_MODE_EN BIT(16)

#define TCS_STATUS_CONTROLLER_IDLE BIT(0)

#define RSC_DRV_ERROR_IRQ_STATUS 0xD0
#define RSC_DRV_ERROR_IRQ_ENABLE 0xD8
#define RSC_DRV_ERROR_IRQ_CLEAR 0xD4

#define EPCB_TIMEOUT_IRQ_EN_MASK BIT(20)
#define EPCB_TIMEOUT_THRESHOLD_SHIFT 0x0
#define EPCB_TIMEOUT_THRESHOLD_MASK 0xFFFF

#define MSGID_READ_OR_WRITE_SHIFT 0x10
#define MSGID_RES_REQ_SHIFT 0x8
#define MSGID_MSG_LENGTH_SHIFT 0x0

#define MSGID_READ 0x0
#define MSGID_WRITE 0x1

#define MSGID_MSG_LENGTH_VALUE 0x8

#define ADDR_SLV_ID_SHIFT 0x10
#define ADDR_OFFSET_SHIFT 0x0

#endif /* __RPMH_HWIO_H__ */
20 changes: 20 additions & 0 deletions core/drivers/qcom/rpmh/nord/rpmh_target_config.h
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@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

#ifndef __RPMH_TARGET_CONFIG_H__
#define __RPMH_TARGET_CONFIG_H__

#include <platform_config.h>

enum rpmh_tcs_config {
RPMH_TCS_AMC = 0, /* Active TCS start */
RPMH_TCS_SLEEP = 2, /* Active TCS end, Sleep TCS start */
RPMH_TCS_WAKE = 3, /* Sleep TCS end, Wake TCS start */
RPMH_TCS_MAX = 4 /* Wake TCS end, Max TCS count */
};

#define RPMH_MAX_CMDS_PER_TCS 16

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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26

@shvm-ap Shivam Sanjay (shvm-ap) Sep 16, 2026

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IDineshChoudhary , the value seems to be 27 based on (TCS_STRIDE and TCS_CMD_STRIDE value). But it is being assigned to .cmds in rpmh_drv_config, whose value in both nord TZ as well as Uefi (drv_config) is 16. I believe that the name "MAX_CMDS" is either misleading or we need to follow 26/27 as you suggested.


#endif /* __RPMH_TARGET_CONFIG_H__ */
4 changes: 2 additions & 2 deletions core/drivers/qcom/rpmh/rpmh_client.c
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Expand Up @@ -24,6 +24,7 @@
#include "rpmh_hal.h"
#include "rpmh_resource_commands.h"
#include "rpmh_tcs.h"
#include "rpmh_hwio.h"

register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AOP_MSG_RAM_BASE,
CORE_MMU_PGDIR_SIZE);
Expand Down Expand Up @@ -66,7 +67,6 @@ struct client_queue {
};

#define AOP_BOOT_COOKIE 0xA0C00C1E
#define MSG_RAM_SECTION_SIZE 0x10000

struct aop_msg_ram_dict {
uint32_t boot_cookie_offset;
Expand Down Expand Up @@ -242,7 +242,7 @@ static TEE_Result check_aop_init(void)
return TEE_ERROR_GENERIC;
}

dict_addr = base + AOP_MSG_RAM_SIZE - MSG_RAM_SECTION_SIZE;
dict_addr = base + 15 * MSG_RAM_SECTION_SIZE;

@IDineshChoudhary IDineshChoudhary Sep 14, 2026

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same comment as #55

dict = (struct aop_msg_ram_dict *)dict_addr;
cookie_addr = base + dict->boot_cookie_offset;

Expand Down
1 change: 1 addition & 0 deletions core/drivers/qcom/rpmh/rpmh_hal.c
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Expand Up @@ -8,6 +8,7 @@
#include <util.h>

#include "rpmh_hal.h"
#include "rpmh_hwio.h"

static struct {
vaddr_t rsc_base;
Expand Down
39 changes: 0 additions & 39 deletions core/drivers/qcom/rpmh/rpmh_hal.h
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Expand Up @@ -17,45 +17,6 @@ enum hal_status {
HAL_STATUS_INVALID_PARAM = 2,
};

#define DRV_STRIDE 0x10000
#define RSC_DRV_IRQ_ENABLE 0x0d00
#define RSC_DRV_IRQ_STATUS 0x0d04
#define RSC_DRV_IRQ_CLEAR 0x0d08

#define RSC_DRV_TCS_CONFIG 0x0C
#define TCS_BASE_OFFSET 0x0D10 /* CMD_WAIT_FOR_CMPL base */
#define TCS_STRIDE 0x2A0

#define TCS_CONTROL_OFFSET 0x04
#define TCS_STATUS_OFFSET 0x08
#define TCS_CMD_ENABLE_OFFSET 0x0C

#define TCS_CMD_BASE_OFFSET 0x20
#define TCS_CMDn_MSGID_OFFSET 0x00
#define TCS_CMDn_ADDR_OFFSET 0x04
#define TCS_CMDn_DATA_OFFSET 0x08
#define TCS_CMD_STRIDE 0x14

#define TCS_CONTROL_AMC_MODE_TRIGGER BIT(24)
#define TCS_CONTROL_AMC_MODE_EN BIT(16)

#define TCS_STATUS_CONTROLLER_IDLE BIT(0)

#define RSC_DRV_ERROR_IRQ_STATUS 0xD0
#define RSC_DRV_ERROR_IRQ_ENABLE 0xD8
#define RSC_DRV_ERROR_IRQ_CLEAR 0xD4

#define EPCB_TIMEOUT_IRQ_EN_MASK BIT(20)
#define EPCB_TIMEOUT_THRESHOLD_SHIFT 0x0
#define EPCB_TIMEOUT_THRESHOLD_MASK 0xFFFF

#define MSGID_READ_OR_WRITE_SHIFT 0x10
#define MSGID_RES_REQ_SHIFT 0x8
#define MSGID_MSG_LENGTH_SHIFT 0x0

#define ADDR_SLV_ID_SHIFT 0x10
#define ADDR_OFFSET_SHIFT 0x0

enum hal_status hal_rpmh_init(vaddr_t rsc_base);
enum hal_status hal_rpmh_register_drv(enum rsc_drv_id drv_id);
enum hal_status hal_rpmh_read_config(enum rsc_drv_id drv_id,
Expand Down