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This patch adds the basic board init routines that invoke the common and mach-snapdragon specific SPL frameworks to proceed with the hand over from boot rom to the next stage i.e. U-Boot proper. This also provides the linker script to generate the SPL image in the format expected by the boot rom. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add a local copy of the nord SoC and board device tree sources (nord.dtsi, nord-ride.dts, nord-rrd.dts, nord-embedded.dtsi and nord-gearvm.dtsi) along with the required clock and interconnect dt-bindings headers. Wire nord-ride.dtb into the build to enable early nord platform bring-up in U-Boot until the DTS files are available upstream. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord Global Clock Controller (GCC). Implement the qcom,nord-gcc driver to provide clocks, resets and power domains required by nord peripherals. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord NE Global Clock Controller (NEGCC). Implement the qcom,nord-negcc driver to provide clocks, resets and power domains required by nord peripherals during initialization. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord SE Global Clock Controller (SEGCC). Implement the qcom,nord-segcc driver to provide clocks, resets and power domains required by nord peripherals during boot. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord NW Global Clock Controller (NWGCC). Implement the qcom,nord-nwgcc driver to provide clocks, resets and power domains required by nord peripherals. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord TCSR Clock Controller (TCSRCC). Implement the qcom,nord-tcsrcc driver to provide the clocks and resets required by nord platform peripherals. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Enable the GCC, NEGCC, SEGCC, NWGCC and TCSRCC clock controller drivers in qcom_defconfig so support for the nord platform is built as part of the shared Qualcomm target configuration. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add a dedicated defconfig for the nord platform. Enable the drivers and board configuration options required to boot nord-based targets in U-Boot. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add support for the nord Top Level Mode Multiplexer (TLMM). Implement the qcom,nord-tlmm pinctrl driver to provide pin configuration support required by nord peripherals. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add nord-ride-u-boot.dtsi to describe the UFS PHY clocks and ufs_mem_phy node required by U-Boot's UFS driver. This allows the UFS controller to probe successfully on the nord-ride platform. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…ate clocks on nord Several NEGCC/GCC gate clocks incorrectly used enable_mask = BIT(0) instead of their actual bit position in a shared multi-bit vote register. Fix enable_reg/enable_mask for 14 GCC and 2 NEGCC clocks to match the kernel driver. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
CONFIG_REMAKE_ELF's u-boot.elf link step used the toolchain's default page-size flags, and its .lds carried no 4K alignment padding, so TME's IMGAUTH rejected the image for misaligned segments. Add a REMAKE_ELF_LDSCRIPT default for ARCH_SNAPDRAGON pointing at a Snapdragon-specific .lds that pads .data to a 4K boundary, so this applies to any Snapdragon board using CONFIG_REMAKE_ELF, not just nord. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
CONFIG_REMAKE_ELF_LDSCRIPT alone leaves u-boot.elf linked with the toolchain's default page-size flags. Set LDFLAGS_u-boot-elf to the same 4K granule flags used for u-boot.bin, for any ARCH_SNAPDRAGON board, not just nord. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
ufs_mem_hc's phys property references ufs_mem_phy, but it is added disabled and nothing else enables it, so UFS never probes. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…gion nord.dtsi's reserved-memory has no SMEM carveout, and nord has no qcom,smem node (the kernel doesn't need one here). U-Boot's SMEM driver needs both to locate the region, so add them mirroring EDK2's own SMEM reservation. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
nord's partition table references host IDs higher than the existing SMEM_HOST_COUNT=30, causing partition enumeration to fail with 'bad host'. Raise SMEM_HOST_COUNT to 256 and report the offending value when it is still too small. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…gion cap configure_reserved_memory() passed raw reg values straight to mmu_change_region_attr_nobreak(), which works at 4K granularity and spins forever on sub-page regions (nord has 0x80-byte SCMI shmem mailboxes two-to-a-page). Page-align every region instead. Also raise N_RESERVED_REGIONS as nord's reserved-memory node has more entries than previously supported boards, and add a guard in set_regions() so an unmappable granule is reported instead of hanging. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…entry
build_mem_map() only emitted entries for the reported DRAM banks,
leaving gaps between banks with no page-table entry at all. On
nord, firmware carves out sub-regions from the SMEM usable-RAM
table, leaving such gaps, and configure_reserved_memory() panics
if a DT reserved-memory node ever falls inside one ('PTE ... should
be a table').
Emit a separate MT_DEVICE_NGNRNE entry for each gap, matching the
attrs already used for the pre-DRAM peripheral block, plus
PTE_BLOCK_RO since nothing should ever legitimately write to an
unlisted, firmware-carved gap. This keeps gaps un-cacheable,
non-executable and read-only while still giving them a mapped,
splittable block entry. Any DT reserved-memory node that falls
inside a gap still gets its own explicit attrs from
configure_reserved_memory() (which overwrites the whole attrs mask,
RO bit included), so this only affects the parts of a gap with no
DT node. Bump rbx_mem_map[] so there's room for a gap entry between
every bank.
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
nord-gearvm.dtsi overrides qupv3_0/1/2, uart4, uart15 and ufs_mem_hc
to only the SoC-specific compatible strings, dropping the generic
qcom,geni-se-qup/geni-uart/geni-debug-uart/ufshc fallback that
upstream convention keeps as the last entry.
serial_msm_geni.c's geni_set_oversampling() checks for the generic
string directly rather than walking the whole compatible list, so
without the fallback no UART driver ever binds ('UART node must be
a child of geniqup node').
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…vation errors boot_fdt_handle_region() now reports every non-zero lmb return code as an ERROR, whereas the prior implementation silently ignored -EEXIST and -EINVAL. On boards with DRAM gaps (e.g. SA8797P Ride), several reserved-memory nodes legitimately hit -EINVAL, flooding the boot log. Restore the original suppression. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
qcom_geni_fw_initialise() was unconditionally registered on EVT_LAST_STAGE_INIT for non-SPL builds. Add CONFIG_QCOM_GENI_FW_LOAD to make this optional, and disable it by default in qcom_defconfig for boards that don't need GENI firmware loading. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
This series adds initial U-Boot support for the Qualcomm nord platform
The commit 0debfe4801bb ("mach-snapdragon: Kconfig: changes / additions to
support SPL") auto selects options that may not be applicable to all
platforms. This results in warning messages during make xxx_defconfig
and/or waiting for user input for on/off or values for certain configs.
So auto select options based on the enabled configs in xxx_defconfig.
Fixes: 0debfe4801bb ("mach-snapdragon: Kconfig: changes / additions to support SPL")
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
This reverts commit 3635906. Signed-off-by: Abhilash V <abhilash.v@oss.qualcomm.com>
Add structure and enum definitions to be able to parse the information that is passed from PBL. This will be used to identify the boot medium. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Save the boot parameters passed from the boot rom and use that to identify the boot device. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Update the SMEM with the boot device information got from the boot rom. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add routines to enable U-Boot SPL to be able to proceed with the boot from MMC partitions. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Setup the malloc base and limit for the SPL to be able to use the memory allocation APIs. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Identify the boot media loader driver and load the FIT image that has the binaries to initialize the DDR, U-Boot proper etc. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
The U-Boot SPL loads the next stage FIT image into internal SRAM. The binaries are 'external' in this FIT image. The SPL has to load the DDR init binary, i.e. qclib and the DDR parameters i.e. qcconfig used by qclib and invoke the qclib. SPL and qclib exchange information using the interface table described in doc/board/qualcomm/interface-table.rst. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Introduce a defconfig for the Qualcomm IPQ5210 SoC based RDPs. Presently supports eMMC. Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
index.rst: - Include 'spl-qclib.rst' rdp.rst: - Add details about the SPL & U-Boot proper build steps, converting to flashable images, source URLs for the needed binaries and scripts. - Update author e-mail id. spl-qclib.rst: - Describe the SPL - Qualcomm Library (QCLib) interface used to exchange information between U-Boot SPL and QCLib for initializing the DDR. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
The boot rom expects the secondary boot loader in MBN format followed by the TME executable. Add rules to board/qualcomm/config.mk to create u-boot-spl.mbn and u-boot-spl.melf. u-boot-spl.melf is the combined multi-elf file that has u-boot-spl.mbn followed by the TME executable. Additionally, this patch adds a config option to specify the path of the TME executable to be used to create u-boot-spl.melf. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Signed-off-by: Abhilash V <abhilash.v@oss.qualcomm.com>
qcom_configure_capsule_updates() had a non-static inline body in a header when CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not set. Any TU including qcom-priv.h got a duplicate symbol at link time. Mark the stub 'static inline' to scope it per-TU. Signed-off-by: Abhilash V <abhilash.v@oss.qualcomm.com>
Gopinath Sekar (g-sekar)
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Upgrading uboot-spl from v4 to latest v8 series.
v8 upstream link: https://lore.kernel.org/u-boot/20260722-spl-v8-v8-0-cbfa79e85a9d@oss.qualcomm.com/