[qcom-next] Revert SPL support for Qualcomm Snapdragon SoCs (PR #77, #79, #85)

arch/arm/Kconfig

@@ -1146,13 +1146,12 @@ config ARCH_SNAPDRAGON
 	select SPMI
 	select BOARD_LATE_INIT
 	select OF_BOARD
-	select SAVE_PREV_BL_FDT_ADDR if !ENABLE_ARM_SOC_BOOT0_HOOK && !SPL
-	select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK && !SPL
+	select SAVE_PREV_BL_FDT_ADDR if !ENABLE_ARM_SOC_BOOT0_HOOK
+	select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
 	select SYSRESET
 	select SYSRESET_PSCI if !QCOM_SNAGBOOT_MODE
 	select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR
 	select MMU_PGPROT
-	select SUPPORT_SPL
 	imply OF_UPSTREAM
 	imply CMD_DM
 	imply DM_USB_GADGET

arch/arm/dts/lemans-evk-u-boot.dtsi

@@ -1,18 +1,20 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 / {
-	clocks {
-		/* Fixed clocks needed by GCC */
-		xo_board_clk {
-			bootph-all;
-		};
-
-		sleep_clk {
-			bootph-all;
-		};
+	/* Will be removed when bootloader updates later */
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ee00000>,
+		      <0x0 0xc0000000 0x0 0x0fd00000>,
+		      <0xD 0x00000000 0x2 0x54100000>,
+		      <0xA 0x80000000 0x1 0x80000000>,
+		      <0x9 0x00000000 0x1 0x80000000>,
+		      <0x1 0x00000000 0x3 0x00000000>,
+		      <0x0 0xd0000000 0x0 0x01900000>,
+		      <0x0 0xd3500000 0x0 0x2cb00000>;
 	};
 
 	/* IMEM boot cookie + TCSR HW version offsets */
@@ -27,40 +29,10 @@
 	};
 };
 
-&ufs_mem_hc {
-	bootph-all; /* Enable UFS for SPL */
-};
-
-&ufs_mem_phy {
-	bootph-all;
-};
-
-&gcc {
-	bootph-all; /* Enable GCC for SPL */
-};
-
-/* RPMH clock controller - required by GCC */
-&rpmhcc {
-	bootph-all;
-};
-
-/* Apps RSC - parent of rpmhcc and rpmhpd */
-&apps_rsc {
-	bootph-all;
-};
-
-/* UART10 - console serial port */
-&uart10 {
-	bootph-all;
-};
-
-&tlmm {
-	bootph-all;   /* Make TLMM GPIO controller available in SPL */
-};
-
 /* Enter Qualcomm EDL/download mode via "reset -edl". */
 &{/psci} {
 	reboot-mode {
 		mode-edl = <0x80000000 0x00000001>;
 	};
 };
+

arch/arm/mach-snapdragon/Kconfig

@@ -42,20 +42,6 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
-config SPL_QCOM_BOOT_FROM_PBL
-	bool "U-Boot SPL is loaded directly by PBL"
-	depends on SPL
-	default y
-	help
-	  Enable this option when U-Boot SPL is loaded directly by PBL (Primary
-	  Boot Loader). In this case, PBL passes boot parameters via r0 register
-	  containing a pointer to pbl_shared_data structure.
-
-	  Disable this option when U-Boot SPL is loaded by XBL or another
-	  intermediate bootloader (e.g., PBL->XBL->U-Boot SPL). In such cases,
-	  the r0 register won't contain valid PBL shared data, and boot device
-	  detection will use fallback mechanisms.
-
 config QCOM_FIT_MULTIDTB
 	bool "Enable FIT multi-DTB selection for Qualcomm platforms"
 	depends on FIT
@@ -97,14 +83,6 @@ config QCOM_EL2_GUNYAH_EXIT_SUPPORT
 
 endchoice
 
-config SPL_WRAPPER_ELF
-	bool "Create wrapper ELF for applicable platforms"
-	depends on SPL
-	help
-	  Some platforms embed the U-Boot SPL binary within an ELF as a segment.
-	  Additional tools are used to convert this ELF into an image that is
-	  usable for the boot ROM.
-
 config QCOM_BOOT0_SNAGBOOT_MODE
 	bool "boot0.h initialization for Snagboot mode"
 	help

arch/arm/mach-snapdragon/Makefile

@@ -2,11 +2,8 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
-ifndef CONFIG_XPL_BUILD
 obj-y += board.o dram.o
 obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
 obj-$(CONFIG_QCOM_FIT_MULTIDTB) += qcom_fit_multidtb.o
 obj-$(CONFIG_QCOM_HWDETECT) += qcom_hwdetect.o
 obj-$(CONFIG_OF_LIVE) += of_fixup.o
-endif
-obj-$(CONFIG_SPL_BUILD) += spl.o

arch/arm/mach-snapdragon/qcom-priv.h

@@ -39,56 +39,5 @@ void qcom_configure_capsule_updates(void) {}
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
 int qcom_parse_memory(const void *fdt, bool fdt_is_internal);
-enum pbl_shared_data_param_id {
-	PSD_ID_PBL_FW_VERSION			= 0x0,	/* PBL firmware version */
-	PSD_ID_PBL_PATCH_VERSION		= 0x1,	/* Patch version */
-	PSD_ID_RMB_MBOX_BASE_ADDR		= 0x2,	/* Not used */
-	PSD_ID_CPU_BOOT_SPEED_HZ		= 0x3,	/* CPU boot speed (Hz) */
-	PSD_ID_BOOT_MEDIA_TYPE			= 0x4,	/* Boot media type */
-	PSD_ID_IS_EDL_MODE			= 0x5,	/* Emergency Download mode */
-	PSD_ID_DEV_PROG_ELF_ENTRY_ADDR		= 0x6,	/* Not used */
-	PSD_ID_XBL_CONFIG_ELF_ENTRY_ADDR	= 0x7,	/* Not used */
-	PSD_ID_XBL_SC_EXT_ELF_ENTRY_ADDR	= 0x8,	/* Not used */
-	PSD_ID_PBL_TIMESTAMPS_BUFFER_ADDR	= 0x9,	/* PBL logs address */
-	PSD_ID_PBL_TIMESTAMPS_BUFFER_SIZE	= 0xa,	/* PBL log size */
-	PSD_ID_PBL_DEBUG_SHARED_INFO_ADDR	= 0xb,	/* Debug info address */
-	PSD_ID_PBL_DEBUG_SHARED_INFO_SIZE	= 0xc,	/* Debug info size */
-	PSD_ID_TME_CPU_PBL_ROM_BYPASS_FUSE	= 0xd,	/* Secure boot status */
-	PSD_ID_XBL_SC_DEBUG_LOG_ADDR		= 0xe,	/* XBL SC debug log address */
-	PSD_ID_XBL_SC_DEBUG_LOG_SIZE		= 0xf,	/* XBL SC debug log size */
-	PSD_ID_CURRENT_IMAGE_SET		= 0x10,	/* Booted image set */
-	PSD_ID_MEDIA_DATA_INFO_ADDR		= 0x11,	/* Media info pointer */
-	PSD_ID_MEDIA_DATA_INFO_SIZE		= 0x12,	/* Media info size */
-	PBL_SHARED_DATA_PARAM_MAX,
-	PBL_SHARED_DATA_PARAM_SIZE	= 0xffffffffu, /* to force 32 bits */
-};
-
-enum pbl_boot_flash_type {
-	PSD_NO_FLASH		= 0,
-	PSD_NOR_FLASH		= 1,
-	PSD_NAND_FLASH		= 2,
-	PSD_ONENAND_FLASH	= 3,
-	PSD_SDC_FLASH		= 4,
-	PSD_MMC_FLASH		= 5,
-	PSD_SPI_FLASH		= 6,
-	PSD_PCIE_FLASH		= 7,
-	PSD_UFS_FLASH		= 8,
-	PSD_RSVD_1_FLASH	= 9,
-	PSD_USB_FLASH		= 10,
-	PSD_SPI_NAND_FLASH	= 11,
-	PSD_SPI_FLASH_GPT	= 12,
-};
-
-struct pbl_shared_data_entry {
-	u32 param_id;
-	ulong value;
-	bool valid;
-};
-
-struct pbl_shared_data {
-	u32 version;
-	u32 num_of_entries;
-	struct pbl_shared_data_entry entry[PBL_SHARED_DATA_PARAM_MAX];
-};
 
 #endif /* __QCOM_PRIV_H__ */