feature: accelerate plain-height tiled conv and depthwise on CMSIS-NN

[asteinh]

Summary

CMSIS-NN accelerated no tiled spatial op: cmsis_tiled_spatial_uses_reference blanket-routed
every tiled conv/depthwise/pool to the reference kernel, so a model TiGrIS tiles to fit (the
flagship MobileNetV2, DS-CNN, AD, TS) ran its convolutions on s8_ref on the Cortex-M boards.
ESP-NN already accelerates a plain height tile; this brings CMSIS-NN to parity. First substep of
Phase 1.5 (native tile-contract acceleration).

Change

• cmsis_tiled_spatial_uses_reference (tigris_kernels_s8.c): unit-dilation CONV/DEPTHWISE are
  no longer blanket-routed to reference when tiled; they run on the CMSIS-NN adapter. Dilated
  tiles still use reference (native dilated-tile parity is a later step); pooling stays on
  reference. Rolled and 2D-width tiles are still routed to reference by tigris_accel_try_s8_ref
  upstream, so only a plain height tile reaches the adapter.
• adapt_conv2d / adapt_depthwise_conv2d (tigris_kernels_cmsis_nn.c): read the tile context
  (tile.in_h, tile.out_h, tile.pad_top) when tile.active. The bottom pad is implicit --
  CMSIS-NN clips input rows at or past IH to the input zero-point -- so an asymmetric edge-tile
  pad needs no pre-pad buffer. Width is never tiled on this path.
• test_accel_routing.c: a plain-height unit-dilation conv/depthwise tile routes to the adapter;
  dilated, rolled, and 2D-width tiles still route to reference.

Testing

• Routing unit tests: 45 passed.
• Host CMSIS-NN differential (host_cmsis_validate: real CMSIS-NN vs the reference dispatcher
  through the executor, so a tiled plan exercises the adapter under tiling): a tiled 3x3 conv at
  stride 1 and stride 2 (the latter exercising asymmetric edge-tile bottom pads) and a tiled
  depthwise conv all report max_abs_diff=0 (bit-exact) vs reference; the untiled control is
  unchanged. Before the adapter fix the tiled plan corrupted the heap (full-tensor dims written
  into tile-sized buffers), confirming the path is now exercised.
• Full runtime unit suite green; the adapter compiles against the CMSIS stub; the stack-usage
  gate passes locally. MISRA and coverage run in CI.

Follow-up

The persistent CI differential (a tiled conv case in tigris-bench host-validation) lands with
the core-versions.json re-pin after this merges, per the standard bench re-pin flow.