fix: size the ESP-NN conv pad-bounce buffer tile-aware so tiled edge tiles accelerate

[asteinh]

Summary

On-device validation (ESP32-S3, SiliconRig) after Phase 1.5 showed tiled convs reach the ESP-NN
adapter with correct output but many EDGE tiles fall back to s8_ref. Root cause:
tigris_esp_nn_prepare sized the asymmetric-pad bounce buffer (s_pad_buf) only when the FULL op
is asymmetric, but tiling manufactures asymmetric edge tiles (a top tile pads only the top; a left
width tile only the left) even for a symmetric full op (e.g. pad 1,1,1,1). Those edge tiles need
the bounce buffer, find it unallocated, and drop to s8_ref. This sizes the pad buffer tile-aware.

Change

• esp_conv_tile_input_dims(): for a conv op, returns the max input rect it sees at inference -
  the tile's input rect (from the stage's tile plan: tile_height, and for 2D the width packed in
  _reserved & 0xFFFF; for a chain, chain_tile_h plus one halo per chain member) - or the full
  tensor if untiled.
• tigris_esp_nn_prepare: for a tiled conv, size max_pad for the tile's input rect with the op's
  pads, so every edge tile's bounce buffer is allocated. Bounded by the tile, not the full op, so
  the memory footprint is preserved (the flagship's fit story is not affected).
• The conv scratch is unchanged: ESP-NN im2col scratch is ~kernel x IC, independent of H/W, so the
  full-op size already covers any tile. Depthwise uses implicit clipping (no bounce) and is
  unaffected.

Validation (real ESP32-S3 via SiliconRig)

• Before: chain_lb (rolled) sram=104 / fallback=52; wide (2D) sram=130 / fallback=338.
• After: both report fallback=0 - every tiled conv takes the ESP-NN adapter.
• Output stays bit-exact vs untiled esp_nn: rolled max_abs_diff=0, 2D max_abs_diff=0.
• Compiles clean for Xtensa (first ESP build of the tile paths, so this also compile-checked the
  1.5b/c ESP code).
• Host is unaffected (the ESP adapter is #ifdef'd out); MISRA baseline unchanged; stack gate
  passes.

Note: on these synthetic 1-row-tile plans the esp_nn-vs-s8_ref speedup is 1.0x (tiles too small to
vectorize). The acceleration benefit shows on real models tiled to the SRAM budget (larger tiles) -
the accelerated multi-board bench capstone.