2D (H x W) spatial tiling: axis, solver, serialization, and gate

[asteinh]

Summary

Adds the compiler side of true 2D (height and width) spatial tiling. When a
stage's minimum 1D-height tile (a single output row) still exceeds the fast
budget, the compiler now solves a 2D tile_h x tile_w shape with halo on both
axes and emits it under a new HW tile axis, so a high-resolution convolution
that previously fail-closed becomes tileable and runs bit-exact. If even the
minimum 2D tile does not fit, compilation fails closed with a distinct
diagnostic.

Pairs with the runtime change in raws-labs/tigris-runtime#31, which executes the
2D plan. Merge tigris-runtime#31 first: the cross-repo gate below builds the
sibling runtime.

What changed

• TILE_AXIS_HW = 3, a 2D receptive-field computation (both kernel axes), and a
  tile solver that picks a feasible (tile_h, tile_w) using the same
  proportional model as the 1D path. 2D is attempted only as a fail-closed
  rescue, when the 1D single-row tile is infeasible.
• 2D eligibility is restricted to standalone single-spatial-op rank-4 stages.
  Binary ops (Add, Mul) and Concat are excluded: the runtime loads every stage
  input with the spatial op's input rectangle, which is not guaranteed to be
  co-tiled with an independent second operand, so admitting such a stage could
  read the wrong region. This mirrors the existing rank-3 length-tiling guard.
• The tile plan serializes axis = HW and packs tile_width into the existing
  reserved field (no wire-format layout change); the reader decodes it. An
  even-2D-infeasible stage produces a distinct "minimum 2D tile" compile error.
• A cross-repo differential gate case set: a high-resolution conv (float and
  int8) compiled at a budget where 1D is infeasible but 2D fits, run through the
  runtime and checked against ONNX Runtime, with the height and width chosen so
  partial edge and corner tiles are exercised; plus a Conv-then-Sigmoid case for
  the pointwise-wrapped path.

Testing

• pytest: full suite passes (319 passed, 2 skipped).
• Cross-repo gate: all existing cases pass, and the new float_2d_tiled_conv,
  int8_2d_tiled_conv, and float_2d_tiled_conv_sigmoid cases match ONNX
  Runtime (float allclose 1e-5; int8 at the established 1-LSB QDQ tolerance),
  with the emitted plan asserted to be axis = HW and multi-tile on both axes.