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1. UART-Tx-Rx-Loopback UART-Tx-Rx-Loopback Public

   Fully functional UART system in Verilog HDL with transmitter (TX), receiver (RX), baud-rate generator, and top-level loopback. Demonstrates precise timing synchronization, deterministic mid-bit sam…

   Verilog 1

2. ALU-8-bit-RegFile ALU-8-bit-RegFile Public

   Modular 8-bit CPU in Verilog with a linear 9-bit instruction architecture - featuring ALU, Register File, Datapath, Control Unit, Instruction Memory and Program Memory.

   Verilog

3. FIR-Filter FIR-Filter Public

   16-tap fixed-point FIR low-pass filter in Verilog, with pipelined MAC datapath, coefficient ROM and shift-register taps. Includes a self-checking testbench with built-in reference model and wavefor…

   Verilog 1

4. Two-Stage-Miller-OpAmp-Design Two-Stage-Miller-OpAmp-Design Public

   Design and optimization of a CMOS Two-Stage Miller Op-Amp using Cadence Virtuoso. Achieved 72dB gain and 63° Phase Margin with optimized stability

5. Differential-to-Single-Ended-Amp-5T Differential-to-Single-Ended-Amp-5T Public

   Implementation and characterization of a 5-Transistor (5T) Differential to Single Ended Amplifier. Analyzes gain (51dB), bandwidth (7.3MHz) and slew rate in a unity-gain buffer configuration using …

6. QPSK-Receiver-with-Synchronous-FIFO-Buffer QPSK-Receiver-with-Synchronous-FIFO-Buffer Public

   RTL design and verification of a QPSK Receiver integrated with a Synchronous FIFO. Implemented in Verilog, featuring hard-decision demapping, ASCII byte assembly and elastic buffering.

   Verilog