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[SM90] Optimize FP8 MegaMoE across L2 epilogue, 4WG launch heuristic and decode swap-AB - #69

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[SM90] Optimize FP8 MegaMoE across L2 epilogue, 4WG launch heuristic and decode swap-AB#69
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@Helicoplacoidea Helicoplacoidea commented Aug 2, 2026

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Summary

Relative to the dev branch, this PR applies three groups of performance optimizations to the SM90 FP8 MegaMoE kernel, covering the L2 epilogue, the 4WG (split-MN) launch heuristic, and the decode swap-AB path.

Main changes:

  • Eliminate shared-memory bank conflicts in the L2 epilogue via an 8-column-granularity XOR swizzle, applied symmetrically on both the STS write and LDS read sides; the permutation is self-cancelling.
  • Refine the 4WG launch threshold to depend on both intermediate_hidden and GPU model (SM count). On H20 + pro (intermediate_hidden >= 3072), where the smaller SM count makes register spilling costly, prefer 2WG (only launch 4WG when >512 tokens/expert); on H200 keep the original >=64 threshold and stay 4WG-first.
  • Extend the swap-AB decode path from BLOCK_N=128 to BLOCK_N=256 (2-WG N-split, each WG driving two m64n64 slabs), and fix the L1-output TMA descriptor to cover the full tile rather than degrading to wg_l1_out_block_n = 64.

Performance

Notes:

  • Baseline: dev branch vs this PR.
  • Hardware: 8× H20-3E.
  • Two configs: DS-V4 Flash (256 experts) / Pro (384 experts).
  • speedup = latency(baseline) / latency(this PR).

Flash shape (256 experts)

tokens baseline us this PR us speedup
1 113.5 106.5 1.07×
2 163.8 161.0 1.02×
4 215.9 213.2 1.01×
8 256.2 250.2 1.02×
16 290.7 285.3 1.02×
32 313.7 303.0 1.04×
64 362.3 335.0 1.08×
128 440.4 431.0 1.02×
256 528.9 526.5 1.00×
512 873.7 873.4 1.00×
1024 1648.6 1648.0 1.00×
2048 2860.5 2881.1 0.99×
4096 5217.7 5197.6 1.00×
8192 9856.1 9822.7 1.00×

Pro shape (384 experts)

tokens baseline us this PR us speedup
1 278.2 259.1 1.07×
2 392.5 349.0 1.12×
4 651.6 591.1 1.10×
8 779.5 722.6 1.08×
16 1024.8 945.4 1.08×
32 1127.0 1027.0 1.10×
64 1178.5 1080.8 1.09×
128 1319.7 1231.6 1.07×
256 1617.5 1614.3 1.00×
512 3012.1 2462.4 1.22×
1024 4695.2 4008.4 1.17×
2048 7894.0 7121.3 1.11×
4096 13711.7 13177.7 1.04×
8192 25845.9 25646.0 1.01×

Pro sees a ~7–18% latency reduction across t16–t1024 (1.22× peak at t512); Flash sees ~2%/8% in the decode range (t16/t64). t256 sits on the threshold-switch boundary; t2048 still gains ~10% (Pro), while t4096+ is essentially flat near the bandwidth/compute ceiling.

Accuracy

All three changes are performance-only and do not change numerical results; accuracy is consistent with the dev branch:

  • L2 epilogue bank swizzle: the 8-column XOR permutation is applied symmetrically on STS/LDS and is self-cancelling, so the column order written to global memory is unchanged.
  • 4WG launch threshold: only changes which kernel shape is selected per shape; each shape independently accumulates the full-tile GEMM, so the result is mathematically equivalent.
  • swap-AB extended to BLOCK_N=256: performs the same GEMM with FP32 accumulation and unchanged K-order, splitting the original m64n128 into two m64n64 slabs.

Single-operator and model-level accuracy validations match the dev branch, with no accuracy regression.

Helicoplacoidea and others added 8 commits July 30, 2026 11:35
…l lambda

Replace the inlined swizzle computation in the swapAB STS write path
with calls to the existing swiz_col(row, col) lambda, matching the
non-swap STS write and LDS scatter read paths. Removes the
swiz_col_0/swiz_col_1 locals that collided in naming with the lambda.

Computation is bitwise-identical; no numerical or behavior change.

Co-Authored-By: Claude <noreply@anthropic.com>
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