Verilog HDL Toolkit

Author: Sanat Konda

A structured and reusable Verilog HDL project demonstrating parameterized hardware design, automated simulation, and self-checking testbenches. This repository provides verified implementations of core digital components (like FIFOs, adders, and multiplexers), accompanied by ModelSim TCL scripts for streamlined compilation and waveform analysis.

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Repository Purpose

This repository serves as both a personal Verilog HDL toolkit and a teaching reference for reusable design and verification practices. It’s built to help engineers and students quickly set up ModelSim simulations, explore parameterized module design, and understand how to create robust self-checking testbenches. All files are written for clarity, modularity, and direct reusability in larger FPGA or ASIC workflows.

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Quick Start

Run these commands in ModelSim to compile and simulate any testbench:

# Navigate to the repository
cd <path_to_repo>

# Compile all Verilog source files
do tcl_for_modelsim/project_compilation.tcl

# Run a specific testbench (example)
vsim work.tb_sync_fifo
run -all

(Optional) Load a preconfigured waveform layout:

do tcl_for_modelsim/run_wave.tcl

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Repository Overview

Folder/File	Description
tcl_for_modelsim/	Contains TCL automation scripts for compiling and running Verilog projects in ModelSim.
test_benches/	Includes self-checking Verilog testbenches for verifying reusable HDL modules.
toychest_pkg.vh	A lightweight Verilog include file containing small reusable modules such as adders and multiplexers.
README.md	Documentation for the repository.

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Components

toychest_pkg.vh

A portable Verilog include file that acts as a reusable module library. Currently includes:

• full_adder — parameterized generic-width full adder
• mux2to1 — 2-to-1 multiplexer

To include it in a source file:

`include "../toychest_pkg.vh"

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tcl_for_modelsim/

project_compilation.tcl

Reusable TCL script that:

• Creates and maps the work library (if missing)
• Compiles all .v files in the current directory
• Prints a confirmation message after compilation

Usage:

do tcl_for_modelsim/project_compilation.tcl

run_wave.tcl

Optional script to configure ModelSim’s waveform window automatically. It can preload signal groups, set radix, and organize simulation views.

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test_benches/

tb_sync_fifo.v

A self-checking testbench for a parameterized synchronous FIFO module.

Features:

• Intelligent randomized stimulus generation with FIFO-aware bias
• Software scoreboard for functional reference
• One-cycle latency verification for registered output paths
• Automatic result checking using $fatal on mismatches
• Readable logging and debugging outputs

Key Concept Demonstrated: Self-checking verification using behavioral reference models.

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tb_full_adder.v

A parameterized testbench for verifying a generic-width full adder module.

Features:

• Tests all input combinations
• Automatically compares expected and actual outputs
• Displays mismatches with descriptive messages

Key Concept Demonstrated: Exhaustive combinational logic testing and reusable testbench structure.

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tb_mux_2to1.v

A testbench designed to verify the 2-to-1 multiplexer module.

Features:

• Systematically tests all combinations of input signals (D0, D1, and S)
• Compares expected output with actual DUT output
• Displays errors using $display for mismatched results

Key Concept Demonstrated: Verification of basic combinational logic behavior through directed stimulus.

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Design Principles

• Fully parameterized Verilog modules
• Each module has its own self-contained, reusable testbench
• TCL scripting used for compile and simulation automation
• Code structured for readability and portability
• Compatible with ModelSim, QuestaSim, and Vivado simulators

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Running Simulations (Detailed Example)

1. Open ModelSim and navigate to the repository:

   cd <path_to_repo>

2. Compile all Verilog files:

   do tcl_for_modelsim/project_compilation.tcl

3. Launch a testbench:

   vsim work.tb_sync_fifo

4. Run the simulation:

   run -all

5. (Optional) Apply waveform settings:

   do tcl_for_modelsim/run_wave.tcl

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Example Simulation Output

[20000] Starting FIFO Test
[25000] wr_en=1 rd_en=0 d_in=0x5F d_out=0x00 full=0 empty=1 count=1
[35000] wr_en=1 rd_en=1 d_in=0xA3 d_out=0x5F full=0 empty=0 count=1
[45000] wr_en=0 rd_en=1 d_in=0xD2 d_out=0xA3 full=0 empty=0 count=0
[75000] Test Complete. All Checks Passed

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Educational Value

This repository demonstrates:

• Clean HDL design using parameterized Verilog
• Testbench-driven verification methodology
• Practical use of TCL automation for simulation management
• Implementation of self-checking verification environments
• Integration of reusable Verilog “package” concepts through include files

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Future Additions

• UART TX/RX module and testbench
• Debouncer and register file modules
• ALU and shift register designs
• Extended TCL macros for waveform grouping and simulation management

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Author

Sanat Konda University of Florida — Electrical and Computer Engineering Focus Areas: FPGA Design, Embedded Systems, Digital Verification