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2 changes: 1 addition & 1 deletion .github/workflows/run_mypy.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ on: [pull_request, push]
jobs:
run_mypy:

runs-on: ubuntu-20.04
runs-on: ubuntu-22.04

steps:
- uses: actions/checkout@v1
Expand Down
33 changes: 23 additions & 10 deletions chb/app/AppResultFunctionMetrics.py
Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,7 @@ def metrics_to_string(
self,
shownocallees: bool = False,
space: str = " ",
hide: List[str] = [],
tags: List[str] = [],
taglen: int = 0) -> str:
callcount = ''
Expand All @@ -251,13 +252,25 @@ def metrics_to_string(
if self.unresolved_call_count > 0:
unrc = str(self.unresolved_call_count)
if len(tags) > 0:
ftags = (" [" + ",".join(tags) + "]").ljust(taglen)

return (str(self.faddr).ljust(10) + space
+ '{:6.1f}'.format(self.espp) + space
+ '{:6.1f}'.format(self.readsp) + space
+ '{:6.1f}'.format(self.writesp) + space
+ unrc.rjust(6) + space
+ str(self.block_count).rjust(6) + space
+ str(self.instruction_count).rjust(6) + space
+ '{:8.3f}'.format(self.time) + ftags + name + callcount)
ftags = space + ("[" + ",".join(tags) + "]").ljust(taglen)
espp = "" if "esp" in hide else space + '{:6.1f}'.format(self.espp)
readsp = "" if "reads" in hide else space + '{:6.1f}'.format(self.readsp)
writesp = ("" if "writes" in hide
else space + '{:6.1f}'.format(self.writesp))
unrcp = ("" if "unrc" in hide else space + unrc.rjust(6))
blocksp = ("" if "blocks" in hide
else space + str(self.block_count).rjust(6))
instrsp = ("" if "instrs" in hide
else space + str(self.instruction_count).rjust(6))
timep = "" if "time" in hide else space + '{:8.3f}'.format(self.time)
return (str(self.faddr).ljust(10)
+ espp
+ readsp
+ writesp
+ unrcp
+ blocksp
+ instrsp
+ timep
+ ftags
+ name
+ callcount)
32 changes: 16 additions & 16 deletions chb/app/AppResultMetrics.py
Original file line number Diff line number Diff line change
Expand Up @@ -518,24 +518,24 @@ def analysis_to_string(self) -> str:
lines.append('-' * 80)
return '\n'.join(lines)

def header_to_string(self, space: str = " ") -> str:
def header_to_string(self, space: str = " ", hide: List[str] = []) -> str:
lines: List[str] = []
lines.append('-' * 80)
h_esp = "" if "esp" in hide else space + "esp".center(6)
h_reads = "" if "reads" in hide else space + "reads".center(6)
h_writes = "" if "writes" in hide else space + "writes".center(6)
h_unrc = "" if "unrc" in hide else space + "unrc".center(6)
h_blocks = "" if "blocks" in hide else space + "blocks".center(6)
h_instrs = "" if "instrs" in hide else space + "instrs".center(6)
h_time = "" if "time" in hide else space + "time".center(8)
lines.append(
'function '
+ space
+ 'esp'.center(6)
+ space
+ 'reads'.center(6)
+ space
+ 'writes'.center(6)
+ space
+ 'unrc'.center(6)
+ space
+ 'blocks'.center(6)
+ space
+ 'instrs'.center(6)
+ space
+ 'time'.center(8))
"function "
+ h_esp
+ h_reads
+ h_writes
+ h_unrc
+ h_blocks
+ h_instrs
+ h_time)
lines.append('-' * 80)
return '\n'.join(lines)
2 changes: 1 addition & 1 deletion chb/app/CHVersion.py
Original file line number Diff line number Diff line change
@@ -1 +1 @@
chbversion: str = "0.3.0-20250401"
chbversion: str = "0.3.0-20250404"
2 changes: 1 addition & 1 deletion chb/arm/ARMInstruction.py
Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ def xdata(self) -> InstrXData:

@property
def mnemonic_stem(self) -> str:
return self.opcode.mnemonic
return self.opcode.mnemonic_stem

@property
def mnemonic(self) -> str:
Expand Down
4 changes: 4 additions & 0 deletions chb/arm/ARMOpcode.py
Original file line number Diff line number Diff line change
Expand Up @@ -241,6 +241,10 @@ def __init__(
def mnemonic(self) -> str:
return self.tags[0]

@property
def mnemonic_stem(self) -> str:
return self.mnemonic

def annotation(self, xdata: InstrXData) -> str:
return self.__str__()

Expand Down
66 changes: 55 additions & 11 deletions chb/arm/opcodes/ARMBitFieldClear.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
# ------------------------------------------------------------------------------
# The MIT License (MIT)
#
# Copyright (c) 2021-2023 Aarno Labs LLC
# Copyright (c) 2021-2025 Aarno Labs LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
Expand All @@ -30,7 +30,7 @@
from chb.app.InstrXData import InstrXData

from chb.arm.ARMDictionaryRecord import armregistry
from chb.arm.ARMOpcode import ARMOpcode, simplify_result
from chb.arm.ARMOpcode import ARMOpcode, ARMOpcodeXData, simplify_result
from chb.arm.ARMOperand import ARMOperand

import chb.arm.ARMPseudoCode as APC
Expand All @@ -41,11 +41,34 @@
import chb.invariants.XXprUtil as XU

import chb.util.fileutil as UF

from chb.util.IndexedTable import IndexedTableValue
from chb.util.loggingutil import chklogger

if TYPE_CHECKING:
from chb.arm.ARMDictionary import ARMDictionary
from chb.invariants.XVariable import XVariable
from chb.invariants.XXpr import XXpr


class ARMBitFieldClearXData(ARMOpcodeXData):
"""Data format:
- variables:
0: vrd

- expressions:
0: xrd
"""

def __init__(self, xdata: InstrXData) -> None:
ARMOpcodeXData.__init__(self, xdata)

@property
def vrd(self) -> "XVariable":
return self.var(0, "vrd")

@property
def xrd(self) -> "XXpr":
return self.xpr(0, "xrd")


@armregistry.register_tag("BFC", ARMOpcode)
Expand All @@ -60,10 +83,8 @@ class ARMBitFieldClear(ARMOpcode):
args[2]: width
args[3]: msb position

xdata format: a:vxrdh
---------------------
vars[0]: lhs (Rd)
xprs[0]: rhs (Rd)
xdata format
------------
rdefs[0]: rhs
uses[0]: lhs
useshigh[0]: lhs
Expand Down Expand Up @@ -102,8 +123,9 @@ def width(self) -> int:
return self.args[2]

def annotation(self, xdata: InstrXData) -> str:
lhs = str(xdata.vars[0])
rhs = str(xdata.xprs[0])
xd = ARMBitFieldClearXData(xdata)
lhs = str(xd.vrd)
rhs = str(xd.xrd)
assignment = (
lhs
+ " := bit-field-clear("
Expand All @@ -112,13 +134,16 @@ def annotation(self, xdata: InstrXData) -> str:
+ str(self.lsb)
+ ", " + str(self.width)
+ ")")
return xd.add_instruction_condition(assignment)
'''
if xdata.has_unknown_instruction_condition():
return "if ? then " + assignment
elif xdata.has_instruction_condition():
c = str(xdata.xprs[1])
return "if " + c + " then " + assignment
else:
return assignment
'''

def ast_prov(
self,
Expand Down Expand Up @@ -149,6 +174,22 @@ def ast_prov(
bytestring=bytestring,
annotations=annotations)

rdefs = xdata.reachingdefs
astree.add_expr_reachingdefs(ll_op1, [rdefs[0]])

# high-level assignment

xd = ARMBitFieldClearXData(xdata)

if not xd.is_ok:
chklogger.logger.error(
"BFC: Encountered error value for rhs at address %s", iaddr)
return ([], [ll_assign])

lhs = xd.vrd
rhsop = xd.xrd

'''
lhsasts = XU.xvariable_to_ast_lvals(lhs, xdata, astree)
if len(lhsasts) == 0:
raise UF.CHBError("BitFieldClear (BFC): no lval found")
Expand All @@ -170,8 +211,11 @@ def ast_prov(
+ ", ".join(str(v) for v in rhsasts))

hl_rhs1 = rhsasts[0]
'''

hl_rhs = astree.mk_binary_op("band", hl_rhs1, maskconst)
hl_lhs = XU.xvariable_to_ast_lval(lhs, xdata, iaddr, astree)
hl_rhsop = XU.xxpr_to_ast_def_expr(rhsop, xdata, iaddr, astree)
hl_rhs = astree.mk_binary_op("band", hl_rhsop, maskconst)

hl_assign = astree.mk_assign(
hl_lhs,
Expand All @@ -184,7 +228,7 @@ def ast_prov(
astree.add_instr_mapping(hl_assign, ll_assign)
astree.add_instr_address(hl_assign, [iaddr])
astree.add_expr_mapping(hl_rhs, ll_rhs)
astree.add_expr_mapping(hl_rhs1, ll_op1)
astree.add_expr_mapping(hl_rhsop, ll_op1)
astree.add_lval_mapping(hl_lhs, ll_lhs)
astree.add_expr_reachingdefs(ll_rhs, [rdefs[0]])
astree.add_expr_reachingdefs(ll_op1, [rdefs[0]])
Expand Down
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