Digital Logic Design & 4-Bit Synchronous Counter (Verilog HDL & TTL Hardware)

🎓 Academic Project Disclaimer: This repository is an educational laboratory project developed for the Digital Logic Design (DLD) course in the BS Cyber Security degree program at University of Engineering and Technology (UET) Lahore. It documents Verilog HDL simulation modeling, state transition analysis, TTL logic gate IC pinouts, and physical breadboard circuit implementation.

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📷 Physical Hardware Prototyping Proof

Breadboard Prototype Top View	Breadboard Wiring & IC Logic Gates

🎥 Watch Real-World Video Demonstration of Hardware Operation

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📐 1. Project Overview & Objectives

Digital counters are fundamental sequential logic building blocks utilized in microprocessor clock division, frequency synthesis, instruction pointers, and hardware state machines.

Key Objectives

• Translate Boolean algebra functions and flip-flop excitation equations into Verilog HDL code.
• Validate state transitions ($0 \rightarrow 1 \rightarrow \dots \rightarrow 15 \rightarrow 0$) using automated Verilog testbenches.
• Wire and debug physical TTL 74xx series IC logic chips on a solderless breadboard.
• Verify real-world LED output state transitions against theoretical Boolean models.

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🔬 2. Theory & Working Principle

Synchronous vs. Asynchronous Counters

• Asynchronous (Ripple) Counter: Flip-flops are clocked sequentially in a ripple cascade. This creates propagation delay accumulation ($n \cdot t_{pd}$), causing dangerous glitch states during high-speed operations.
• Synchronous Counter: All flip-flops share a single common clock input line ($\text{CLK}$). State transitions occur simultaneously on the positive clock edge, guaranteeing zero propagation delay skew and high-speed signal integrity.

graph TD
    CLK[Common Clock Input Signal] -->|Positive Edge Trigger| FF0[Flip-Flop 0 Q0 - LSB]
    CLK -->|Positive Edge Trigger| FF1[Flip-Flop 1 Q1]
    CLK -->|Positive Edge Trigger| FF2[Flip-Flop 2 Q2]
    CLK -->|Positive Edge Trigger| FF3[Flip-Flop 3 Q3 - MSB]

    FF0 -->|Q0 Enable| AND1[AND Gate 1]
    FF1 -->|Q1 Enable| AND1
    AND1 -->|Q0 AND Q1| AND2[AND Gate 2]
    FF2 -->|Q2 Enable| AND2

Loading

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📊 3. State Transition Table

Present State ($Q_3 Q_2 Q_1 Q_0$)	Decimal	Reset ($R$)	Next State ($Q_3^+ Q_2^+ Q_1^+ Q_0^+$)	Output Decimal	State Description
0000	0	0	0001	1	Initial State
0001	1	0	0010	2	Increment
0010	2	0	0011	3	Increment
0011	3	0	0100	4	Increment
0100	4	0	0101	5	Increment
0101	5	0	0110	6	Increment
0110	6	0	0111	7	Increment
0111	7	0	1000	8	Increment
1000	8	0	1001	9	Increment
1001	9	0	1010	10	Increment
1010	10	0	1011	11	Increment
1011	11	0	1100	12	Increment
1100	12	0	1101	13	Increment
1101	13	0	1110	14	Increment
1110	14	0	1111	15	Maximum Count
1111	15	0	0000	0	Overflow Wrap-Around
XXXX	X	1	0000	0	Active-High Synchronous Reset

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💻 4. Verilog HDL Implementation

4-Bit Synchronous Counter Module (verilog/digital_counter.v)

`timescale 1ns / 1ps

module digital_counter (
    input  wire       clk,    // Clock input signal (Positive-edge triggered)
    input  wire       rst,    // Synchronous Reset signal (Active-High)
    output reg  [3:0] count   // 4-Bit Output Register (Q3 Q2 Q1 Q0)
);

    // Synchronous positive-edge clock logic
    always @(posedge clk) begin
        if (rst) begin
            count <= 4'b0000;   // Reset counter output to binary 0
        end else begin
            count <= count + 1'b1; // Increment counter by 1 (wraps 15 -> 0)
        end
    end

endmodule

Verilog Simulation Testbench (verilog/tb_digital_counter.v)

`timescale 1ns / 1ps

module tb_digital_counter;
    reg clk;
    reg rst;
    wire [3:0] count;

    digital_counter uut (
        .clk(clk),
        .rst(rst),
        .count(count)
    );

    always #5 clk = ~clk; // 100MHz clock cycle generation

    initial begin
        $monitor("Time=%0t ns | rst=%b | count=%b (%0d in decimal)", $time, rst, count, count);
        clk = 0; rst = 1; #15;
        rst = 0; #160;
        rst = 1; #10;
        rst = 0; #30;
        $finish;
    end
endmodule

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🧪 5. Simulation Traces & Execution Logs

=== STARTING 4-BIT SYNCHRONOUS COUNTER SIMULATION ===
Time=0 ns   | rst=1 | count=xxxx (x in decimal)
Time=5 ns   | rst=1 | count=0000 (0 in decimal)
Time=15 ns  | rst=0 | count=0000 (0 in decimal)
Time=25 ns  | rst=0 | count=0001 (1 in decimal)
Time=35 ns  | rst=0 | count=0010 (2 in decimal)
...
Time=165 ns | rst=0 | count=1111 (15 in decimal)
Time=175 ns | rst=0 | count=0000 (0 in decimal) [OVERFLOW WRAP-AROUND]
Time=175 ns | rst=1 | count=0000 (0 in decimal) [SYNCHRONOUS RESET ASSERTED]
=== SIMULATION COMPLETED SUCCESSFULLY ===

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🛠️ 6. Hardware Components & Circuit Setup

Hardware BOM (Bill of Materials)

• Breadboard: Solderless prototype breadboard.
• Integrated Circuits (ICs):
  • 7408: Quad 2-input AND gate (Logic steering).
  • 7432: Quad 2-input OR gate.
  • 7404: Hex Inverter.
  • 7476 / 7474: Dual JK / D Flip-Flops.
• Input Controls: SPST toggle switches with $10\text{k}\Omega$ pull-down resistors.
• Output Indicators: 4x LEDs with $330\Omega$ current-limiting resistors.
• Power Supply: $+5.0\text{V DC}$ regulated power supply.

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📁 7. Repository Layout

digital-logic-design/
├── .github/
│   └── dependabot.yml              # Automated monthly dependency scanner
├── assets/
│   ├── screenshots/                # Breadboard prototype hardware photos
│   │   ├── circuit_board_top.jpeg
│   │   └── circuit_board_wiring.jpeg
│   └── video/                      # Hardware operational video proof
│       └── hardware_demo.mp4
├── docs/
│   ├── BOOLEAN_ANALYSIS.md         # Flip-flop excitation equations
│   ├── DESIGN_NOTES.md             # Signal integrity & decoupling notes
│   └── TRUTH_TABLES.md             # Complete state transition tables & IC pinouts
├── schematics/
│   └── logic_circuit.mermaid       # Mermaid logic circuit schematics
├── simulation/
│   ├── output_log.txt              # Simulation output execution log
│   └── simulation_notes.md         # Waveform breakdown notes
├── verilog/
│   ├── digital_counter.v           # 4-Bit Synchronous Counter Verilog Module
│   ├── tb_digital_counter.v        # Automated Simulation Testbench
│   └── README.md                   # Icarus Verilog compilation guide
├── CODE_OF_CONDUCT.md              # Contributor Code of Conduct
├── CONTRIBUTING.md                 # Contribution guidelines
├── LICENSE                         # MIT License
├── README.md                       # Portfolio Documentation Page
└── SECURITY.md                     # Hardware Security Policy

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🎓 8. Learning Outcomes

1. Hardware Description Languages (Verilog HDL): Implemented synchronous edge-triggered register logic and automated simulation testbenches.
2. Boolean Circuit Optimization: Derived flip-flop excitation equations using K-Maps.
3. Physical Hardware Prototyping: Assembled TTL logic ICs on solderless breadboards, implementing floating input mitigation ($10\text{k}\Omega$ pull-down resistors) and decoupling capacitors.

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📄 License & Author

Distributed under the MIT License. See LICENSE for details.

Author: Tahniat Farhan — BS Cyber Security, UET Lahore.