Missing signal opts #3264
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Missing signal opts #3264
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@shlmregev @veblush I am confused about the include files referencing something called Note: the experimental |
…nsorflow#3269) * Sync files related to Reverse_V2 from TFLite tensorflow#3110 * PRelu Int16x8 support in RefC * Fix code style in prelu_test.cc * 1. Reverted the copyright year * Resolved compilation error for Int8x8 test case * Add Dynamic_Update_Slice support to TFLM * Code style error correction * Code style correction * Replaced hard coded MaxDimensions to RuntimeShape::kMaxSmallSize * 1. Added more test cases \n2.Removed unused code * Updates for test failure on ARM * Code style updates * Updates on test case failure for ARM * Updates on test case failure for ARM * Code style updates * Add Reduce_All reference operator support to TFLM * Resolving HiFi build errors --------- Co-authored-by: Esun Kim <veblush@google.com>
Switch-cases in decode_state_lut.cc don't assign a default value to a local variables. On one version of ARM GCC (building for ARM cortex m33, this results in a compiler error [-Werror=maybe-uninitialized]. BUG=451462435
* Add Ingenic MIPS port to README.md * Update README.md Changed order of new board to be alphabetical * Update README.md Removed extra brackets making things look wrong. --------- Co-authored-by: Esun Kim <veblush@google.com>
1. When building with old Xtensa toolchains, the compiler throw an unused variable warning which is treated as error (-Werror is defined by default). The cause is ScopedMicroProfile instantiation in the decoder op. Added a dummy reference to mute the warning. 2. Old pre C++14 Xtensa compilers don't support ticks in preprocessor constants, e.g. 0x8000'0000 Removed the ticks. BUG=451462435
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Add missing optimizations for xtensa/ and hexagon/ to frontend ops under signal/
BUG=315941833