Hope you coverage all my repos. Welcome!
Hello there, I'm a Design Verification Engineer, and have a keen interest in anything and everthing VLSI! I am a working professional and currently working on project(s) and exploring.
- Verilog
- System Verilog
- UVM
- Xilinx Ise
- Cadence Xcelium
- Cadence SimVision
- vManager
- QuestaSim
- Synopsys VCS
- Cadence Virtuoso
Thank you for visiting