Phase 1: establish Rev A hardware contract and PCB

[danielbrownjr]

Summary

This draft PR tracks Jump Jet Phase 1 hardware definition and first Rev A PCB implementation.

It is intentionally open before the PCB is complete so schematic corrections, mechanical decisions, footprint work, component selections, layout rationale, and validation evidence can accumulate in one reviewable place.

This PR is not fabrication-ready and does not authorize heater or fan actuation. The production firmware remains cold-safe and heater-incapable.

Current Phase 1 status

Completed / established:

• Phase 0 cold-safe firmware foundation merged to main
• Rev A.4.1 reviewed as the authoritative schematic baseline
• authoritative Rev A.4.1 KiCad project source checked into the repository
• Phase 1 hardware source-of-truth register established
• CZ4060 standalone characterization recorded; 24 V / 200 W / 8.33 A remains the conservative design basis and approximately 189 W / 7.89 A was measured sustained
• ESP32-S3 Super Mini physically identified; Pin 1, body, USB shell, pitch evidence, castellation width, and one longitudinal registration datum recorded
• provisional project-local castellated receiving footprint added; production use still requires process review and a 1:1 physical fit check
• direct castellated mounting and a solid isolation-controlled carrier beneath the module selected as current directions
• native four-wire PWM/tach fan architecture selected
• provisional four-wire fan schematic interface implemented
• Sanyo Denki 9GA0424P3J001 retained for prototype characterization only
• Q1, F2, and J2 candidate parts identified
• power architecture separated conceptually into +5V_SYS/GATE and isolated/source-selected +5V_MCU
• heater gate-drive default-OFF requirements clarified
• PCB design established as active Phase 1 implementation, not missing-artifact recovery

Current important design directions

Heater path

Current topology:

+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> external CZ4060 heater -> Q1 -> GND

The heater path is sized using the conservative 8.33 A basis until production-intent validation proves otherwise.

ESP32-S3 mounting

Current physical evidence:

• module PCB body: 23.67 × 17.91 mm
• overall length including USB-C: 25.07 mm
• USB-C overhang: approximately 1.40 mm
• USB shell: 8.84 mm wide × 3.12 mm high, occupying 7.48 mm over the module PCB
• 18 castellations, nine per side
• nominal 2.54 mm pitch and 15.24 mm row spacing
• measured castellation width: 1.96 mm
• non-USB PCB edge to near edge of first castellation: 1.00 mm
• Pin 1 physically identified

Production direction:

• direct castellated soldering to SMD carrier lands
• provisional footprint exists but receiving-land/process geometry remains open
• underside is flat with no mounted components
• exposed underside contacts/test pads require electrical isolation
• solid carrier PCB is currently preferred
• a central cutout is not required by current evidence and will be reconsidered only if later cleaning, inspection, thermal, assembly, or mechanical evidence supports it
• optional locating holes must be physically validated or deliberately omitted
• mandatory 1:1 physical fit verification before footprint freeze

ESP32 power

Preferred architecture:

protected 24 V -> onboard regulator -> +5V_SYS/GATE
                                  -> isolated/source-selected +5V_MCU -> ESP32

USB-C is retained for service, flashing, recovery, and debug—not normal installed power. USB-only power must not energize gate drive. Mixed-source topology and backfeed behavior remain fabrication blockers.

Fan architecture

The original Rev A.4.1 two-wire low-side-switched fan-power block is obsolete for production. Phase 1 now implements provisional schematic provisions for:

• continuous fused 24 V fan power
• continuous ground
• four-position JST-XH connector as a strong candidate, with mating direction still provisional
• separate open-drain PWM using a 2N7002-class provisional transistor and direct gate pulldown
• separate 3.3 V tach pull-up/series/filter provisions
• PWM and tach test points
• generic, unassigned controller-side nets; no GPIO is frozen

Model-specific manufacturer data confirms 24 V, 21.6–26.4 V operation, 0.27 A, 6.48 W, pulse sensor, and PWM capability for the 9GA0424P3J001. Exact PWM frequency, high-Z/0% behavior, tach output circuit, PPR, startup/minimum duty, RPM/stall behavior, and proof thresholds remain characterization-dependent.

Gate drive

Rev A.4.1 uses SN74AHCT125 buffering with used OE inputs tied low. Required correction remains:

• hardware-default-disabled heater gate drive
• gate-drive circuitry powered only from the 24 V-derived system rail
• USB-only MCU power must not energize Q1 drive
• retain direct Q1 gate pulldown
• qualify partial-power-down behavior
• add test points for gate-driver supply, OE, Q1 gate, and source reference

Mechanics status

• the newer Prusa-derived void is the preferred enclosure-space reference
• the earlier smaller-void system-level incompatibility conclusion is superseded
• the Jetpack fan attachment has a measured local 32 × 32 mm hole pattern, nominal 3.5 mm holes, and approximately 38 mm aperture
• no common installed transform between the void and attachment exports is preserved
• PCB over the cold-air intake is the preferred provisional direction
• an aligned local constraint map is still required before fabrication-intent Edge.Cuts

Current fabrication blockers

• recover the installed transform between the preferred Prusa-derived void and Jetpack attachment datum
• define PCB plane/envelope, mounting holes, connector-facing edges, service zones, USB datum, airflow no-go area, and antenna-open direction
• finish ESP32 receiving-land/process geometry and exact registration
• verify remaining physical pad numbering/labels; Pin 1 is already identified
• map underside contacts and define carrier isolation
• identify antenna and enforce a conservative pre-fabrication keepout
• define USB shell/plug/cable/service envelope
• physically validate or omit locating holes
• verify external 5 V / USB VBUS topology and mixed-source backfeed
• correct heater gate-driver default-OFF behavior
• complete regulator load and thermal analysis
• verify Q1 multipad mapping and F2 holder footprint
• select TF1/TS1 physical implementations
• select J1/F1/MOD1 parts and footprints
• coordinate fuses against production PSU behavior
• qualify four-wire fan connector/interface values and delivered fan behavior
• pass the final 1:1 ESP32 fit check
• run native KiCad project/library resolution and ERC
• run PCB DRC after the first PCB exists

Installed Wi-Fi RSSI/range qualification is post-prototype and pre-release; it does not replace the pre-fabrication antenna identity/keepout requirement.

Phase 1 review checklist

Mechanical / footprint

• Recover installed mechanical transform and local constraint map
• Freeze PCB envelope, mounting holes, connector-facing edges, and service zones
• Measure ESP32 castellation width and longitudinal datum
• Physically identify ESP32 Pin 1
• Verify remaining ESP32 pad numbering/labels
• Map underside contacts and define carrier isolation
• Define antenna identity and conservative keepout
• Define USB-C mechanical/access keepout
• Validate or omit temporary locating holes
• Generate provisional production-direction ESP32 footprint
• Pass 1:1 physical fit check

Power / protection

• Verify external 5 V / USB VBUS topology
• Define reverse-current/source-selection architecture
• Select and qualify 24 V -> 5 V regulator
• Complete 5 V load inventory and chamber-temperature derating
• Correct heater gate-driver default-OFF behavior
• Verify partial-power-down behavior
• Add heater power-domain/OE/gate/source test points
• Coordinate fuse behavior against production PSU limits

Heater path

• Verify Q1 package/symbol/footprint mapping and thermal implementation
• Verify F2 holder footprint
• Select TF1 and TS1 physical implementations
• Confirm J2 production implementation
• Review heater-path copper bottlenecks and high-current return geometry

Fan

• Supersede obsolete two-wire switched-power block
• Implement provisional continuous fused 24 V and ground
• Implement provisional open-drain PWM interface
• Implement provisional 3.3 V tach interface and test points
• Verify delivered lead functions and interface electrical behavior
• Characterize high-Z/0% PWM and compatible frequency range
• Characterize tach waveform and pulses/revolution
• Characterize startup, minimum reliable speed, RPM versus duty, stall, and locked rotor
• Characterize installed airflow, hub temperature, and cooldown
• Derive RPM/stall/proof thresholds from evidence

PCB

• Create first Rev A .kicad_pcb after mechanics close
• Place high-current/safety path first
• Review copper widths, neckdowns, thermal spreading, and pad heating
• Review ground/return strategy, ADC noise exposure, and antenna clearance
• Run KiCad ERC/DRC and 3D/mechanical review
• Complete fabrication-readiness review

Safety boundary

Nothing in this PR authorizes heater or fan actuation.

Firmware remains cold-safe until the hardware path, sensing, fan proof, safety interlocks, and physical protections are implemented and validated. Firmware does not replace fusing, independent thermal cutoff, rated wiring/connectors, MOSFET derating, PCB copper/clearance requirements, airflow validation, or temperature-suitable materials.

Source of truth

• ROADMAP.md
• TODO.md
• docs/HARDWARE_BASELINE.md
• docs/PHASE1_HARDWARE_REGISTER.md
• docs/PRODUCT_SAFETY_CONTRACT.md
• docs/hardware/9ga0424p3j001-characterization.md
• hardware/kicad/JumpJet_RevA/README.md

The hardware register is the living record of confirmed facts, measurements, design decisions, candidates, assumptions, blockers, and validation status.

Merge criteria

Do not merge this PR merely because the first PCB exists. Phase 1 is merge-ready only after the hardware contract is reviewed, critical mappings and safety corrections are resolved, the first PCB is created and reviewed, fabrication blockers are closed or explicitly accepted with evidence, documentation is synchronized, no candidate is silently promoted to BOM-final, and no firmware GPIO/ADC/PWM/RPM/thermal constant is frozen without supporting hardware evidence.