rt: keep MULU.W/DIVU.W operands in data registers - #123
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ami_umul16() and ami_divu32_16_step() gave a u32 to MULU.W and DIVU.W with the constraint "dmi". Those instructions read 16 bits, so when GCC chose the memory alternative they read the high word of the u32 on this big-endian machine: 0 for every operand these routines pass. Under -mregparm=3 it did: ami_divu64_32_soft() multiplied by "mulu.w 36(sp),d1", and every divide with a divisor of 65536 or more came out wrong (udivsi3(0x10000,0x10001) = 1, the rt_test and Emulator failures). Both operands are now "d". Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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ami_umul16()andami_divu32_16_step()used the"dmi"constraint on a u32 operand ofmulu.w/divu.w. Under-mregparm=3GCC spills it, and a memory operand makes the word op read the high half of the big-endian u32. Constraint is now"d".Scope:
-m68000builds only (AMINETXDUO_CPU=any, which both emulator arms boot).-m68020emits no word ops.Proof (vamos,
rt_test, toolchain 16.2.2):Static: main emits
mulu.w 36(sp),d1twice inami_divu64_32_soft; this branch emits 0 memory operands (reproduced by zz9k-fpga, NO BLOCKER).🤖 Generated with Claude Code