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tonykorycki/README.md

Antoni Korycki

Electrical and Computer Engineering student at NYU Tandon.

Currently:

  • FPGA Engineering Intern at ICEYE working with Synthetic Aperture Radar satellites,
  • Designing a radar inference ASIC for the NYU Processor Design Team's 2026–27 SkyWater 130nm tapeout
  • Building a self-balancing robot on ZephyrRTOS + custom PCB for fun
  • Joining the control team of NYU ARC Robotics: Team Ultraviolet this fall

Tech Stack

Hardware

SystemVerilog Verilog VHDL Vitis HLS Vivado Verilator cocotb KiCad

Embedded

C C++ FreeRTOS Zephyr RTOS Mbed Arduino Raspberry Pi

Software / ML

Python MATLAB PyTorch TensorFlow OpenCV NumPy Pandas scikit-learn


LinkedIn

Pinned Loading

  1. kyber-ntt-fpga kyber-ntt-fpga Public

    FPGA hardware accelerator for post-quantum cryptography: NTT polynomial multiplication for CRYSTALS-Kyber (ML-KEM / FIPS 203) on a PYNQ-Z2 Zynq SoC

    Jupyter Notebook 1

  2. fpga-kws-mlp fpga-kws-mlp Public

    Real-time keyword spotting on Artix-7 FPGA streaming 512-pt FFT + quantized INT8 MLP inference in Verilog, trained end-to-end in Python. 98% test + 99% sim accuracy, 91% LUT utilization on Basys 3.

    Verilog

  3. RDT-26-firmware RDT-26-firmware Public

    Firmware and testing code for NYU Robotic Design Team's 2026 Lunar Rover; Running on Teensy 4.1 (32-bit ARM Cortex-M7 @ 600 MHz), uses community port of FreeRTOS for Teensy

    C++

  4. kinetic-key kinetic-key Public

    Gesture combination lock on the STM32L475 Discovery board; Uses 6D Dynamic Time Warping with Sakoe-Chiba and z-score normalization to grade physical gesture replication. Runs on Mbed RTOS.

    C

  5. V-Aid-Climbing V-Aid-Climbing Public

    NYU Prototyping Fund Spring 25 project - CV system for assisting visually impaired climbers; Scans routes, creates 3D tactile route maps, provides LLM-powered audio climbing guidance.

    Python 1

  6. radar-systolic-asic radar-systolic-asic Public

    Radar signal classifier ASIC for NYU Processor Design Team 2026-27 Tapeout (WIP)

    SystemVerilog