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open-ip-portfolio
open-ip-portfolio PublicOpen-source SystemVerilog protocol IP portfolio (Apache-2.0): 117 protocol configurations, 81 distinct cores — synthesizable RTL + self-checking TBs + iverilog/yosys flows, CRV coverage-closed. Edu…
SystemVerilog 1
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open-vip-portfolio
open-vip-portfolio PublicOpen-source UVM Verification IP portfolio: 87 protocol VIPs (AMBA/DDR/PCIe/CXL/USB/MIPI/Ethernet...) with L1-L4 SVA, 100%-gate coverage regression, pyslang elaboration gate & iverilog smoke harness…
SystemVerilog 1
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orca-v63
orca-v63 PublicORCA v6.3 ZEN++ heterogeneous multi-tile SoC and AI accelerator IP: RISC-V RV64GCV out-of-order SMT-4 CPU + NPU, 4x2 NoC mesh, 16 dtypes incl BitNet 1.58b, low-power PMU. 49/49 RTL, 11 coverage-dri…
SystemVerilog
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qpu-sim-suite
qpu-sim-suite PublicQPU Software Simulation Suite - Four simulators, three phases, twelve milestones. Pure NumPy quantum computing simulation platform.
Python 1
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