Common-Centroid Placement Algorithm for IC design elements

Generate folded-cascode opamp parameters with interactive CLI.

Deadlines for Conferences which are relevant to the research topics of E&D

Reference voltage: 315 mV Supply range: 1.0 V -3.3 V Temperature coefficient: ≈ 15 ppm/°C (−40 °C to 125 °C)

Design and simulation of a two-stage CMOS OpAmp in Cadence Virtuoso. Verified via PVT corners and Monte Carlo analysis.

This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

Design, simulation and full verification of a CMOS transimpedance amplifier.

Transistor-level LTspice study of a standard 6T SRAM cell, Single Event Upset fault injection, and a radiation-hardened DICE memory cell for space electronics applications.

CMOS PWM Generator designed and simulated in LTspice. The project demonstrates pulse-width modulation using a behavioral ramp source, transistor-level CMOS comparator, and CMOS output logic operating from a 1.8 V supply. It serves as an early-stage mixed-signal IC design prototype.

Neural Network models for automating design parameters of CS amplifier. Includes automated SPICE data generation and model validation in Python and MATLAB.

MY JOURNEY TO BE AN ANALOG IC ENGINEER . Self-learning projects using industry standard EDA tools. [Work-In-Progress]

Investigation of CMOS bandgap reference operating principles using LTspice simulations. The project demonstrates CTAT and PTAT voltage generation, PTAT current generation, and temperature compensation techniques used in analog integrated circuit design..