eda-playground

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Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl2008 vhdl-testbench eda-playground

A VHDL code base that contains Utility Packages for both HDL and Testbenches

simulation vhdl rtl hdl testbenches osvvm vunit vhdl-modules vhdl-code vhdl-testbench eda-playground

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

simulation vhdl hdl testbenches osvvm vunit vhdl-code vhdl-examples vhdl2008 vhdl-testbench chipdev vhdl-2008 eda-playground

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

fsm fpga hardware simulation verilog computer-architecture icarus-verilog hdl testbench risc-v digital-design processor-design cpu-design eda-playground

encoder uvm uvm-verification eda-playground 4-to-2encoder

labs verilog systemverilog icarus-verilog eda-playground

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