FPGA feed handler — Vitis HLS NASDAQ ITCH 5.0 parser, AOS BRAM order book, 6-cycle parse-to-book pipeline. Benchmarked against C++ baseline (274 ns P99.9).
C++23 low-latency feed handler — DPDK pcap PMD, NASDAQ ITCH 5.0 parser, zero-copy mbuf pipeline, MPSC market data aggregation into SOA order book. Zero heap allocation end-to-end.
UDP multicast market-data simulator & feed handler with controllable impairments, sequence reordering, and per-interval latency percentiles.
Multi-venue crypto order book reconstruction in C++20, verified continuously against exchange checksums
Low-latency market data feed handler in C++20. Zero-copy ITCH-style parser, lock-free SPSC ring buffer, sequence gap recovery, and per-symbol book building with HDR latency instrumentation.
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