ASIC implementation flow infrastructure, successor to OpenLane

FazyRV Hachure is a System on Chip that integrates seven different variants of the bit-serial FazyRV RISC-V core in one chip for testing and research purposes.

KianV GF180 ASIC runs ulinux, linux and XV6

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

ASIC Design Flow of Signed 8x8 Booth-Wallace Multiplier (Radix-4)

High-Efficiency 16-bit BFloat16 Multiply-Accumulate (MAC) Unit for ML Acceleration. Verified for SkyWater 130nm (TinyTapeout 07). Includes FP32 accumulation and streaming I/O.

AI/LLM-assisted circuit design using opensource tools

Simple Systolic array implementation

Chipathon GF180MCU LibreLane examples: 5 hands-on notebooks (counter bare-block, chip-top with macro, workshop slot use, multi-macro counter+ALU) for the chipathon-2026-gf180mcu-padring fork.

Sovryn KAN NPU V2 SG13G2 final freeze with template-native design sources, signoff evidence, and Prometheus v16 signoff-copilot analysis.

Chipathon 2026 workshop padring fork of wafer-space/gf180mcu-project-template - adds a workshop slot mirroring JuanMoya/padring_gf180 as a native LibreLane slot.

Open-source ASIC flow laboratory focused on LibreLane, OpenROAD, Yosys, and open silicon workflows.

Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.

Unified process configuration format for ChipFlow Backend and LibreLane