KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip Star 19 Code Issues Pull requests EE577b-Course-Project verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal Updated May 6, 2020 Verilog
dasbluehole / NOC_MAP Star 7 Code Issues Pull requests Core mapping on to NOC asic noc silicon 2d-mesh networkonchip silicon-fabrication on-chip-network Updated Nov 7, 2019 C
talsania / network-on-chip Star 7 Code Issues Pull requests 4-core mesh noc ip. check out my notes: fpga systemverilog networkonchip Updated Apr 19, 2026 SystemVerilog
cognimachina / SWAN_paper Star 0 Code Issues Pull requests Code and simulation framework accompanying the SWAN NoC paper (NEORV32-based design) interconnect neuromorphic-computing networkonchip Updated Jul 3, 2026 VHDL