This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
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Updated
Nov 24, 2025 - SystemVerilog
This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.
A CPU Simulator
RISC-V assembly with Ripes — tests, pipeline/CPI analysis, forwarding, caches, RGB888→RGB565.
🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.
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