scl180nm

Here are 3 public repositories matching this topic...

DivyamGoyal-github / RISC_V-SoC-Tapeout-Program_VSD_Caravel_IITGN_Phase2

This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.

simulation verification rtl verilog gls synopsys risc-v caravel pdk chip-design functional-simulation scl180nm

Updated Jan 5, 2026
Verilog

ShekharShwetank / RISC-V_Reference_SoC_Tapeout_Program_Phase_2

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RISC-V Reference SoC Design and Tapeout Program Phase 2 personal documentation

asic synopsys risc-v caravel asic-design sky130 system-on-chip-design scl180nm

Updated Feb 19, 2026
Verilog

Rakesh-2306 / Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier

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Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

calibre cadence-virtuoso mixed-signal rf-analysis linearity noise-cancellation stability-analysis low-noise-amplifier lna noise-analysis cadence-spectre s-parameter design-rule-check design-for-manufacturability scl180nm full-custom-layout parasitic-extraction layout-vs-schematic custom-spiral-inductor

Updated Apr 14, 2026

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