sm75

FlashAttention v1 forward pass in CUDA for NVIDIA Turing (SM75)

Veda sparse attention for ComfyUI's MiniMax-H3, with a hand-written CUDA kernel for NVIDIA Turing (sm_75) so it runs on RTX 2080 Ti / GTX 16-series and any compute-capability 7.5 card. Upstream Veda only supports SM80+. Measured on one 2080 Ti: 4.16x at 768x768x124, 1.83x at 512x512x124.

Compiler MVP that detects Transformer fusion patterns, generates optimized CUDA kernels with WMMA Tensor Cores, and executes them on real GPU hardware — 10.5 TFLOPs on RTX 2070, correctness validated against PyTorch.

Backward pass CUDA kernels for fused GEMM+Bias+GeLU on SM75 (Turing). Float4 vectorized WMMA kernels validated against PyTorch autograd. 3.1x faster than autograd at M=1024. 24/24 tests passing.

MX450 (TU117) has no Tensor Core in silicon — a reproducible reverse-engineering case study: Falcon microcode, register-level proofs, and why every HMMA library is 18x slower. 三语文档。

Fork of vLLM carrying the SM75 / Qwen3.8 changes used by qwen3-8-27b-dual-2080ti-vllm (branch 2080ti_dual_qwen38-27B); upstream main is kept as the 'upstream' branch

Instruction-level Tensor Core micro-kernel engineering on SM75 (RTX 2070), including PTX manual emission, shared-memory staging, and hardware-aware auto-tuning.

PyTorch CUDA wheels with sm_75 for AWS g5g (Graviton arm64 / aarch64 + NVIDIA T4G) — fixes 'no kernel image is available' — pip index

Fork of FlashQLA-SM70-SM75 with the SM75 import/build tweaks used by qwen3-8-27b-dual-2080ti-vllm (branch 2080ti_dual_qwen38-27B)

Reproducible FreeToken MoE expert-offload compatibility lab and benchmarks for NVIDIA Turing sm_75.

Qwen3.8-27B 双 RTX 2080 Ti 22GB + NVLink 的 vLLM 部署（上游 main 路线）：SM75 移植、MTP 下保住 FULL cudagraph（单并发解码 54.1→37.5 ms/步）、256K/500K 上下文与 128K tiered offload profile