Full-custom CMOS digital VLSI circuit design & HSPICE simulation portfolio (University of Tehran, Fall 2023): Inverter VTC/timing, thermal leakage, DCVSL/Pseudo-NMOS benchmarking, 6T SRAM SNM butterfly curves, and Tanner L-Edit physical silicon mask layouts.
sram circuit-simulation vlsi cmos ic-design hspice digital-electronics university-of-tehran l-edit tanner-tools
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Updated
Sep 18, 2026 - Roff