ALU with Testbench

Objective

Design and verify an 8-bit Arithmetic Logic Unit (ALU) using Verilog HDL.

Operations Implemented

Select	Operation
000	Addition
001	Subtraction
010	AND
011	OR
100	XOR
101	NOT
110	Left Shift
111	Right Shift

Files

• alu.v : ALU Design
• alu_tb.v : Testbench
• Waveform Screenshot

Simulation

The design was verified using a Verilog testbench. All arithmetic and logical operations were simulated and validated.

Expected Results

• Correct arithmetic operations
• Correct logical operations
• Carry generation during overflow conditions

Author

Prateek Kumar Sahu M.Tech VLSI Design