Quartus Projects

This repository contains Digital System Design projects developed using Intel Quartus Prime, implementing various digital circuits in VHDL and Block Diagram formats.

Repository Structure

Quartus/

Contains three exercises (askisi1-3) for the Digital System Design course:

askisi1/

• Description: VHDL-based digital circuit exercise
• Main Files:
  • askisi1.vhd - VHDL source code
  • askisi1.qpf - Quartus project file
  • askisi1.qsf - Quartus settings file
  • Waveform.vwf - Simulation waveform file
• Documentation: askisi1(a).pdf
• Screenshots:
  • RTL viewer screenshot
  • Compilation results
  • Waveform simulation results

askisi2/

• Description: Block Diagram File (BDF) based exercise
• Main Files:
  • ask2.bdf - Block diagram schematic
  • ask2.qpf - Quartus project file
  • ask2.qsf - Quartus settings file
  • Waveform.vwf - Simulation waveform file
• Documentation: askisi2(a).pdf
• Screenshots:
  • Compilation results
  • Waveform simulation results

askisi3/

• Description: VHDL-based digital circuit exercise
• Main Files:
  • ask3.vhd - VHDL source code
  • ask3.qpf - Quartus project file
  • ask3.qsf - Quartus settings file
  • Waveform.vwf, Waveform1.vwf - Simulation waveform files
• Documentation: askisi3(a).pdf
• Screenshots:
  • RTL viewer screenshot
  • Compilation results
  • Waveform simulation results

Quartus2h/

Contains a comprehensive 2-hour project (ergasia2h) implementing an Arithmetic Logic Unit (ALU) in two parts:

ergasia2h(Part1)/

• Description: Basic ALU implementation with fundamental operations
• Main Files:
  • proto2h.vhdl - Main VHDL source code
  • ergasia2h.qpf - Quartus project file
  • ergasia2h.qsf - Quartus settings file
  • ergasia2h_description.txt - Project description
• Operations Implemented:
  • ADD/SUB (Addition/Subtraction)
  • AND/OR (Logical operations)
  • NAND/NOR (Negated logical operations)
  • XOR/NXOR (Exclusive OR operations)
• Screenshots: Separate waveform screenshots for each operation

ergasia2h(Part2)/

• Description: Advanced 16-bit ALU with hierarchical design
• Main Files:
  • ergasia2h_Part2.vhd - Top-level entity
  • alu_16_bit.vhd - 16-bit ALU implementation
  • alu_1_bit.vhd - 1-bit ALU building block
  • ControlCircuit.vhd - Control circuit for operation selection
  • ergasia2h_Part2.qpf - Quartus project file
  • ergasia2h_Part2.qsf - Quartus settings file
  • ergasia2h_Part2_description.txt - Project description
  • Waveformpart2.vwf - Simulation waveform file
• Features:
  • Modular design with 1-bit ALU components
  • 16-bit operations using structural composition
  • Control circuit for operation selection
  • Comprehensive testing for all operations
• Screenshots: Individual waveform results for ADD, SUB, AND, OR, NAND, NOR, XOR operations, RTL viewer, and compilation results
• Documentation: DSD105(pdf file).pdf - Course documentation

Project Structure

Each project folder contains:

• db/: Database files generated by Quartus
• incremental_db/: Incremental compilation database
• output_files/: Compilation reports, fitting results, and programming files (.pof)
• simulation/:
  • modelsim/: ModelSim simulation files
  • qsim/: Quartus simulator files and waveforms

Tools Used

• Intel Quartus Prime: FPGA design and synthesis
• VHDL: Hardware description language
• ModelSim: Functional simulation
• Quartus Simulator: Timing simulation and waveform analysis

File Types

• .vhd, .vhdl: VHDL source files
• .bdf: Block Diagram Files
• .qpf: Quartus Project Files
• .qsf: Quartus Settings Files
• .vwf: Vector Waveform Files (simulation)
• .pof: Programming Object Files (for FPGA programming)
• .rpt: Compilation and analysis reports

Notes

• All projects have been successfully compiled and simulated
• Screenshots document the RTL designs, compilation results, and simulation waveforms
• PDF documentation provides detailed requirements and specifications for each exercise