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1. Async_FIFO_Design Async_FIFO_Design Public

   This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains every aspects of the code.

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2. RISCV_8bit_pipeline RISCV_8bit_pipeline Public

   Mini-project for the grading of Digital system design with FPGA course - IISc | year 2024. RISC V 8 bit 5 stage pipelined processor verilog code.

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3. PSD_2024 PSD_2024 Public

   This repository consist of my solutions of the assignments of the course Processor System Design E3 245 at DESE IISc Bangalore of year 2024.

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4. HDL-Bits-Solutions HDL-Bits-Solutions Public

   This repo contains HDL-bits solutions. I tried to provide multiple solutions for the same problem, with comments.

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5. TCP-IP-Project-Kavach TCP-IP-Project-Kavach Public

   Mini-project for the grading of TCP/IP Networking course - IISc | year 2023

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6. verilog_practice verilog_practice Public