Skip to content
View vamsireddysup's full-sized avatar

Highlights

  • Pro

Block or report vamsireddysup

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
vamsireddysup/README.md

Hello there, I'm Vamsidhar Reddy Eraganeni

Email LinkedIn GitHub Hardware Engineer Iron Man

Passionate about hardware design verification, formal methods, computer architecture, and building resilient, high-performance hardware systems.


Tech Stack ⚡

SystemVerilog Verilog C/C++ Python TCL UVM QuestaSim Synopsys Vivado Linux

Focus Areas 🔍

Protocols:     I2C · PCIe · AXI · APB · UART · AHB
Architectures: x86 · RISC-V · MIPS-Lite · MESI Coherence
Focus:         RTL Design · UVM · SVA · DFT · Post-Silicon Validation

Featured Projects 🔐

Project Description Tech
PCIe TLP Verification UVM environment for PCIe Transaction Layer Packet generation and checking SV · UVM
I2C Protocol Verification Master-slave I2C verification with open-drain SDA, ACK/NACK, FSM-based controller SV
LLC Cache Simulation 16MB 16-way set-associative LLC with MESI coherence and pseudo-LRU replacement SV
MIPS-Lite Pipeline Simulator Cycle-accurate 5-stage MIPS pipeline with forwarding and hazard detection C
Hardware Multipliers RTL implementations of array, Booth, and Wallace Tree multiplier architectures SV
Post-Silicon Validation DFX and JTAG TAP-based post-silicon debug and test methodology JTAG

Repository Index 📁

Repository Topic
synopsys_uvm_lab UVM lab — packet router DUT, labs 1–6
synopsys_sva_lab SystemVerilog Assertions (SVA) — sequences, properties, formal
synopsys_sv_tb_lab SV testbench methodology
synopsys_rtl_lab RTL synthesis with Synopsys Design Compiler + SAED32
sv-verification-lab SV verification concepts and projects
ece571_systemverilog-for-verification ECE571 — SV for Verification (HW1, HW2)
ece595-emulation-and-functional-verification ECE595 — Emulation and Functional Verification
ece593_hw2 ECE593 HW2 — Cascaded ALU design and verification
ece_593_hw1 ECE593 HW1 — ALU design and testbench
ece587project ECE587 — Architectural simulator project
sem_projects Sustainable Energy Management — Python data analysis
misc-projects Python utility notebooks

Open To 🙃

  • Hardware design/verification internship and full-time opportunities
  • Open-source hardware verification collaborations
  • RISC-V ecosystem and hardware verification communities
  • Discussions on emerging computer architecture trends
Profile Banner
Let's build something bug-free together! 🐞

Popular repositories Loading

  1. ECE510-H4AI ECE510-H4AI Public

    Custom co-processor chiplet accelerating the QK^T attention score computation using FP4 E2M1 multiply and FP32 accumulate on a systolic array, implemented on the Sky130 HD process. The chiplet uses…

    Verilog 1

  2. style-guides style-guides Public

    Forked from lowRISC/style-guides

    lowRISC Style Guides

    1

  3. vamsireddysup vamsireddysup Public

    I'm Vamsidhar Reddy Eraganeni

  4. last-level-cache-simulation last-level-cache-simulation Public

    Simulation of a 16MB, 16-way set-associative Last-Level Cache (LLC) with MESI cache coherence protocol and pseudo-LRU replacement policy.

    SystemVerilog

  5. I2C-Protocol-Verification I2C-Protocol-Verification Public

    SystemVerilog verification environment for an I2C master-slave design, with a constrained-random testbench, scoreboard, SVA assertions, and functional/code coverage. Supports Standard, Fast, and Fa…

    SystemVerilog

  6. ECE_593_HW1 ECE_593_HW1 Public

    SystemVerilog design and functional verification of an Arithmetic Logic Unit (ALU) for ECE 593 — Advanced Verification.

    SystemVerilog