fix(rocm): build the GGUF MoE path on AMD HIP - #1
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Three issues surfaced when serving Qwen3-30B-A3B IQ4_XS through the GGUF loader on an RX 7700 XT: - gguf.py passed nvcc-only flags (--expt-relaxed-constexpr, -ccbin) to hipcc; gate them on HIP like the rest of the JIT builds. - mmvq/moe_vec/gguf_kernel warp-sync calls used 32-bit masks; HIP requires 64-bit. CUDA accepts the 64-bit form too, so switch unconditionally. - layers/activation.py routed GGUF-MoE activations through a triton kernel that fails LLVM register allocation on some RDNA3 shapes; HIP now uses plain torch ops. NVIDIA keeps flashinfer/triton. - kernel/triton/activation.py resolves the HIP probe without relying on the arch helper import. Verified end-to-end on gfx1101/ROCm 7.2: Qwen3-30B-A3B IQ4_XS serves coherently with --moe-backend offload at ~52 tok/s decode. Signed-off-by: Christian Stewart <christian@aperture.us>
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Testing FlashML-org#131 on an AMD Radeon RX 7700 XT (gfx1101, ROCm 7.2) via the HIP port in FlashML-org#137 surfaced issues:
gguf.pypasses nvcc-only flags (--expt-relaxed-constexpr,-ccbin) to the HIP build. hipcc rejects both; relaxed constexpr is already the default under clang.mmvq.cuh,moe_vec.cuh, andgguf_kernel.cupass 32-bit masks. HIP requires 64-bit masks; CUDA accepts the 64-bit form as well, so the change is unconditional.layers/activation.pyroutes GGUF-MoE activations through a triton kernel that fails LLVM register allocation (couldn't allocate output register for constraint 'f') on some RDNA3 shapes. Under HIP this commit falls back to plain torch ops; NVIDIA paths are unchanged.With this PR, Qwen3-30B-A3B IQ4_XS serves coherently with
--moe-backend offloadat approximately 52 tokens/s decode on gfx1101.Limitation: CUDA graph capture triggers additional kernel compilations that hit the same triton codegen failure, so this configuration currently requires
--cuda-graph-max-bs 0.