PCM is a family of power conversion modules for solar-plus-storage systems: a 75 kW non-isolated bidirectional MPPT DC/DC (PV-P75, with a 100/110 kW four-phase build), a 125 kW three-phase battery inverter (PCS-P125, with a four-wire build PCS-P125-4W) and a 60 kW isolated dual-active-bridge DC/DC (DAB-D60). Everything here — KiCad 10 schematics, BOMs, costed BOMs and the simulations behind every component value — is generated by Python scripts in this repository. Nothing is bench-validated: every figure is calculated, simulated or estimated, and is labelled as such.

Documentation · Overview · Cost · Comparison · Risks · Repository guide

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⚡ At a glance

Product	What it is	Rating	Ports	Status as of 2026-10-07
PV-P75	non-isolated bidirectional buck-boost DC/DC with MPPT	75 kW · 82.5 kW max	both 250–1000 V · 135 A	power board PV-PWR rev A2 + control board PV-CTL rev A2 drawn (recorder flash, chainable stop, ready, battery-fault input and status relay added; Ethernet footprints only, D-075); every build check passes; independent review answered (D-065, D-072); 75 kW from 556 V; 74.25 kW at 550 V × 135 A — the current-limited corner (the delivered rating from 562 V at equal port voltages; calculated); DESAT string re-rated to 1,300 V diodes (D-081); BOM 980 / 820 USD
PV-P100/110	four-phase build of the same design	100 / 110 kW	both 250–1000 V · 145 A on the battery port	PV-PWR-4 + PV-CTL drawn; checks pass; a derated build today (100 kW from 690 V, full power to 35 °C inlet); PV-P110's 110 kW is a PV-input rating (108.8 kW delivered A→B); BOM 1,171 / 981 USD
PCS-P125	three-phase bidirectional DC-to-AC battery inverter, three-wire (3W+PE)	125 kW · 150 kVA for 2 min	DC 590–950 V required, 624–950 V calculated at 400 V AC · 400 V AC, 180 A	power board PCS-PWR rev A0 + control board PCS-CTL rev A0 (assembly PCS-CTL-3W) drawn, every build check passes; start-up from the grid through an AC tap and AC precharge, Ethernet (Modbus TCP) fitted (D-074, D-075); control studied by calculation, off-grid accuracy and ride-through included (D-066, D-077); independently re-checked (R2) and corrected at zero BOM cost — trip chain, gate resistor, backup band, start-up sequence, bounded transients (D-078, D-079); re-checked again (R3) — one-coil synchronised close, both trip layers on the four-wire short, PCS / PV bus coordination, two SiC module grades, the declared off-grid envelope (D-080); and once more, economically (R4) — DESAT diodes re-rated to 1,300 V, the battery-less bus window enforced (750 V default, 782 V clamp), the envelope as a declared output capability, full operation from −10 °C inlet, grade B rated 124.57 kW at 60 °C (D-081); BOM 1,589 / 1,349 USD
PCS-P125-4W	the same inverter, four-wire (3W+N+PE), with a fourth two-level leg for the neutral	125 kW · 100 % unbalanced load (one phase at its tier)	DC 650–950 V required, 624–950 V calculated (neutral leg in mode B) · 400/230 V AC, 180 A	power board PCS-PWR-4W rev A0 + PCS-CTL rev A0 (assembly PCS-CTL-4W) drawn, every build check passes (D-074); auxiliary supply re-rated for it (D-076); BOM 1,926 / 1,636 USD (a lower bound: two lines unpriced)
DAB-D60	isolated dual-active-bridge DC/DC	60 kW	590–950 V · 400–900 V	device study with Chinese discretes (not drawn), corrected after the review (D-068); board DAB60 rev B (Wolfspeed modules) frozen, to be redrawn cost-first

_{Ratings: REQUIREMENTS.md (PV-01…08, AC-02, DAB-01, DAB-10/11). BOM figures are catalogue / 5,000 units in USD, estimates where no price exists (bom/COST.md, as of 2026-10-07). The earlier full-featured eight-board platform is kept as the roadmap's reference implementation and is not developed further.}

🔬 Status dashboard

	Requirements	Architecture	Design study	Schematic	Build checks	Costed BOM	Bench test
PV-P75							—
PV-P100/110							—
PCS-P125 / -4W							—
DAB-D60							—

_{Teal = done · amber = partial, in study or frozen · — = not started. Bench tests and PCB layout are outside this repository's scope. Generated detail: Overview › Status. Pin audit: 247 parts drawn, 192 pass (1,961 pins), 0 fail, 55 not auditable with a written reason (pin_audit_report.csv). Review registers: the independent review of commit 033d8d8 — 27 findings, 22 closed, 5 open — is gen/data/review_pcm.csv; the re-check of commit a427981 — 14 findings, all closed in the register — is gen/data/review_r2.csv; the re-check of commit 615e4b5 — 5 findings, all closed in the register — is gen/data/review_r3.csv; the economical re-check of commit 845131d — 12 decision areas, all closed in the register — is gen/data/review_r4.csv; all four summarised in Verification.}

Independent re-check R2 (2026-10-07). A second independent review re-checked commit a427981 and raised 14 findings (8 high, 6 medium). Each was reproduced on our own models before anything changed: 9 Confirmed, 1 Firmware Handled, 2 Already Fixed, 1 Not Applicable, 1 Improvement Recommended (review_r2.csv). D-078 answers the power stage and protection chain — the inverter's trip turns the gates off at about 520 A, so the turn-off gate resistor went from 7.5 to 8.75 Ω (1,437 V against 1,445 V, calculated), the controller's backup band was lowered below the L1 knee, the SiC devices get an absolute R_DS(on) limit with a per-lot derating, and the AC coil and the residual-current monitor get one contract each. D-079 answers the control study — a 1,944-case tolerance regression (the reviewer's own reproduction of the nominal margins matched ours), off-grid transients bounded at 0.43 / 1.77 pu (the 2.17 pu figure is superseded), stiff-grid ride-through without derating (the derating is now the fallback) and the AC start as an executed state machine with five repairs. Nothing was added to the BOM. The installation conditions the modules rely on are collected, row by row with their source lines, in INSTALLATION.md; what only hardware can close stays open in Risks and open items.

Independent re-check R3 (2026-10-07). A third review re-checked the R2 response, commit 615e4b5, and raised five findings (4 high, 1 low): 4 Confirmed, 1 Improvement Recommended, all closed in the register (review_r3.csv). D-080 answers them with firmware and acceptance rules and one requirement row, nothing added to the BOM (simulated or calculated): the inverter's synchronised close now pulls in one AC contactor coil at a time (38.9 / 42.2 W against the 48 W peak; 646 state-event pairs and 24 fault runs pass); the four-wire line-to-neutral short is replayed through both hardware trip layers, and a 5 ms onset clamp keeps it 13.3 A below the lower one; the assumed 50 µs DC/DC stop is replaced by the coupled PCS / PV trajectory, on which an island rides a full-load rejection with the PV modules' coordination row (its one-node 909 V is a model validity, not a rating — the window enforced since D-081 is 750 / 782 V); the SiC devices grade each module A or B with a full tier table (at 60 °C 198.0 / 216.0 / 242.9 A against 179.8 / 192.6 / 192.6 A; grade B's 179.8 A is 124.57 kW at PF 1), bound to the module serial; and the off-grid envelope is the ITIC-style curve from memory, adopted by delegation as requirement AC-04 (+0.054 pu margin, simulated). The reviewer's own inner-loop reruns matched the study to the last digit.

Independent re-check R4 (2026-10-07). A fourth, economical review of commit 845131d grouped its points into twelve decision areas (2 high, 5 medium, 5 low), each with a preferred option, an alternative, a no-change boundary and a cost basis: 3 Confirmed, 4 Already Fixed, 3 Improvement Recommended, 2 Not Applicable, all closed in the register (review_r4.csv). D-081 answers them (calculated or simulated): its one new technical finding was right and our own envelope made it wider — the DESAT string of every 1,700 V gate-drive channel now has two 1,300 V diodes (Vishay BYG23T-M3/TR) instead of 1,000 V ones that relied on unproven sharing, each blocking the 1,130 V static envelope alone, for +0.96 to +2.12 USD per module at 5,000 units; the coupled DC bus carries the inter-module cable (up to +28 V) and runs inside an enforced window — 750 V default, 782 V firmware clamp, no island start above 791 V — over a harness contract for the integrator; requirement AC-04 is reworded as the module's declared output capability, not a load-compatibility claim, with a release sequence; the inverter's passive cold-start table is too small to be useful, so its cold rating is full operation from −10 °C inlet (AC-02 amended by delegation); grade B states its rating, 124.57 kW at 60 °C; and the custom magnetics get an RFQ index (RFQ-MAGNETICS.md). No topology, capacitor bank, brake chopper or inter-module trip line was added. The restrictions it accepts, each with the boundary that stays, are listed in Risks and open items.

Independent closure re-check R5 (2026-10-07). A fifth review of commit 5c56aaa found no new defect: six closure rows, 4 Already Fixed, 1 Not Applicable (the earlier platform's GDRV-HB / DAB60 keep their own 1,200 V-class diode strings, deferred with their own qualification), 1 Improvement Recommended, all closed in the register (review_r5.csv). The reviewer verified D-081 at BOM level (the BYG23T counts per board) and by his own arithmetic (the 6.415–9.365 V DESAT window, the 790.9 V bus permissive, the −10 °C inverter grade), and his bottom line is accepted in D-082: the next useful milestone is a representative switching cell and a controlled prototype, not another declaration that every script passes. What changes is one document: every open gate of the five rounds — the DESAT string's dynamic qualification, the battery-less bus and its harness, the cold rating and grid code, the SiC cell's short-circuit survival, layout, supplier data, magnetics, bench protection tests, pre-compliance, production controls — is consolidated into the Qualification plan: 44 gates Q-01..Q-44 in four stages, each with the acceptance criterion our records give, the test asset and the product or claim it blocks. No hardware change; nothing is measured; no unrestricted HV, full-power or production sign-off is claimed from the script passes.

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🧭 The cost-first PV module

One power board and one control board, control referenced to the negative DC rail, one reinforced barrier to everything a person or another device can touch (ARCHITECTURE-COSTFIRST.md):

%%{init: {"theme": "base", "themeVariables": {"primaryColor": "#EEF3F7", "primaryBorderColor": "#0B1F33", "primaryTextColor": "#0B1F33", "lineColor": "#5B6B7A", "secondaryColor": "#D9F2EF", "tertiaryColor": "#FFF4D6", "fontFamily": "Inter, Helvetica, Arial, sans-serif"}}}%%
flowchart LR
    PV["PV array<br/>250–1000 V"]:::ext
    BAT["battery or DC bus<br/>250–1000 V"]:::ext
    subgraph LIVE["DC side · referenced to BUS−"]
        PA["Port A<br/>varistors · contactor<br/>no fuse, no precharge"]:::live
        PH["3 interleaved buck-boost phases<br/>2 × 1700 V SiC per switch · 32 kHz<br/>12 NSI6651 gate drivers"]:::live
        PB["Port B<br/>aR fuse per pole · contactor<br/>precharge"]:::live
        AUX["75 W flyback<br/>fed from both ports"]:::live
        CTL["controller F280039C<br/>trip latch · watchdog"]:::live
    end
    subgraph SELV["SELV side"]
        COM["CAN · RS-485 · Ethernet option<br/>stop chain · ready · DI1 · relay"]:::selv
        FAN["3 fans"]:::selv
    end
    PV --> PA --> PH --> PB --> BAT
    PA --> AUX
    PB --> AUX
    AUX -- "3.3 V" --> CTL
    CTL <-- "PWM · measurements" --> PH
    CTL == "reinforced barrier B1" ==> COM
    AUX == "SELV winding" ==> FAN
    classDef live fill:#FDE7E0,stroke:#E4572E,color:#0B1F33
    classDef selv fill:#D9F2EF,stroke:#00A99D,color:#0B1F33
    classDef ext fill:#FFFFFF,stroke:#5B6B7A,stroke-dasharray:4 3

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_{Red = hazardous-live DC side · teal = safe extra-low-voltage side. Detail: Architecture, Power stage, Protection and safety.}

💰 Cost

_{Source: bom/COST.md (generated by gen/cost.py) · estimated, nothing quoted}

_{Benchmark: Megarevo's 228 kW string PCS sells for 1,500 USD = 6.6 USD/kW (the owner's figure, a selling price). Source: market_prices.csv, pcs_spec.json, bom/COST.md}

The numbers behind the charts (generated table)

Product	What the figure is	kW	Catalogue USD	USD/kW	5,000 units USD	USD/kW	Evidence	5k ÷ benchmark-equivalent BOM
PV-P75	BOM of drawn boards (PV-PWR + PV-CTL)	75	980	13.1	820	10.9	66 % of catalogue on estimates · 16 % of 5k on published breaks · 1 unpriced line (lower bound)	2.0× (≈ 410 USD)
PV-P100/110	BOM of drawn boards (PV-PWR-4 + PV-CTL)	100 / 110	1,171	11.7 / 10.6	981	9.8 / 8.9	64 % of catalogue on estimates · 16 % of 5k on published breaks · 2 unpriced lines (lower bound)	1.8× / 1.8×
PCS-P125	BOM of drawn boards, three-wire (PCS-PWR + PCS-CTL-3W)	125	1,589	12.7	1,349	10.8	77 % of catalogue on estimates · 9 % of 5k on published breaks · 1 unpriced line (lower bound)	1.8× (≈ 744 USD)
PCS-P125-4W	BOM of drawn boards, four-wire (PCS-PWR-4W + PCS-CTL-4W)	125	1,926	15.4	1,636	13.1	75 % of catalogue on estimates · 9 % of 5k on published breaks · 2 unpriced lines (lower bound)	2.2× (≈ 744 USD)
PCS-P125	design study, 3-wire (two-level, pcs_spec.json); the drawn boards above cost more (D-063)	125	1,431	11.4	1,149	9.2	5 % of 5k on published prices	—
PCS-P125	design study, 4-wire (two-level, pcs_spec.json); the drawn boards above cost more (D-063)	125	1,731	13.8	1,392	11.1	not stated for 4-wire	—
PV-P75 earlier platform	BOM of drawn boards (8 boards)	75	2,836	37.8	2,275	30.3	51 % of catalogue on estimates · 17 % of 5k on published breaks · 7 unpriced lines (lower bound)	5.5×
DAB-D60 earlier platform	BOM of drawn boards (5 boards)	60	3,615	60.2	2,927	48.8	48 % of catalogue on estimates · 12 % of 5k on published breaks · 3 unpriced lines (lower bound)	7.5×
PCS-P125	three-level T-type estimate, withdrawn by D-053	125	1,037	8.3	801	6.4	—	—

_{Generated by figures_overview.py from bom/*_costed_BOM.csv, pcs_spec.json and costfirst_pcs_bom.csv; benchmark arithmetic from gen/cost.py. Do not edit between the markers.}

Method, assumptions and the next cost levers: Sourcing and cost.

📐 Against Megarevo, module for module

The owner's rule (D-073) is parity with the competitor's modules in both directions — whatever its PMA inverter modules and its PMD-75-G3 DC/DC module offer, ours offer too, and the other way round; cabinets, containers, hybrids and HMI panels are discarded, and both products stay bidirectional. Two generated tables compare row by row, calculated against published: PV-P75 against the PMD-75-G3 — 2 better, 24 meets, 3 below, 5 not assessed, 0 pending, out of 34 published rows — and PCS-P125 / PCS-P125-4W against the PMA0125 — 2 better, 38 meets, 4 below, 9 not assessed, 0 pending, out of 53 published rows. The module-level items those tables do not cover (grid type, start-up from the grid, Ethernet, the fault recorder and upgrade, discrete I/O, declarations) are tracked in the register gen/data/megarevo_2026_parity.csv; its gaps were closed by D-074 to D-077 except the altitude, which stays at 2,000 m with a 3,000 m / 5,000 m option specified. Details and the rows below Megarevo: Comparison with Megarevo.

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🧰 How the repository works

Python is the source of truth: simulations write the design values, generators turn them into checked schematics, and the BOMs, costs and these charts are generated from the result. hardware/ and bom/ are never edited by hand.

%%{init: {"theme": "base", "themeVariables": {"primaryColor": "#EEF3F7", "primaryBorderColor": "#0B1F33", "primaryTextColor": "#0B1F33", "lineColor": "#5B6B7A", "secondaryColor": "#D9F2EF", "tertiaryColor": "#FFF4D6", "fontFamily": "Inter, Helvetica, Arial, sans-serif"}}}%%
flowchart LR
    REQ["docs/requirements<br/>scope lock · decisions"] --> SIM["sim/*.py<br/>design + simulation"]
    SIM -- "spec JSON" --> GEN["gen/*.py<br/>one generator per board"]
    LIB["docs/fetch.py<br/>datasheets"] -- "pin tables" --> GEN
    GEN --> HW["hardware/<br/>KiCad 10 · PDF · netlist"]
    HW --> CHK{"build checks<br/>ERC · netlist · domains<br/>stress · BOM"}
    CHK -- "pass" --> BOM["bom/<br/>board BOMs"]
    BOM -- "build_all.py --bom" --> MOD["module BOMs"]
    MOD -- "cost.py" --> COST["costed BOMs<br/>COST.md"]
    COST -- "figures_*.py" --> DOCS["docs/<br/>charts · tables"]

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🧰 Quick start

# 1  Python 3.12 environment
python3.12 -m venv .venv
.venv/bin/pip install numpy scipy matplotlib pyelftools   # PyOpenMagnetics (requirements.txt) is optional: sim/magnetics.py only

# 2  Third-party datasheets and reference designs are not kept in git - the BOM check needs them
.venv/bin/python docs/fetch.py          # downloads every file of docs/SOURCES.csv and verifies its SHA-256

# 3  Build the cost-first PV module: KiCad project, ERC, netlist check, PDF and BOM per board
.venv/bin/python gen/pv_power.py        # PV-PWR and PV-PWR-4
.venv/bin/python gen/pv_ctrl.py         # PV-CTL
.venv/bin/python gen/build_all.py --bom # roll the board BOMs up into module BOMs
.venv/bin/python gen/cost.py            # costed BOMs and bom/COST.md

# 4  Run one simulation; refresh the documentation charts and generated tables
.venv/bin/python sim/pv_design.py
.venv/bin/python docs/assets/figures_overview.py

Tools: KiCad 10 (kicad-cli; on macOS /Applications/KiCad/KiCad.app/Contents/MacOS/kicad-cli) and ngspice 46 on PATH. A few library files must be saved by hand (sites that refuse scripted downloads): the list is in docs/LIBRARY.md. Everything else — every board, audit and simulation — is in the Repository guide.

📚 Repository map

.
├── README.md                this page
├── CLAUDE.md                project rules
├── docs/
│   ├── README.md            documentation hub
│   ├── guide/               the documentation pages
│   ├── assets/              style guide, banner, figure scripts, generated charts
│   ├── requirements/        scope lock, decision register, architecture specifications
│   ├── reference-designs/   vendor reference designs (documents fetched, READMEs in git)
│   ├── datasheets/          component datasheets (fetched, not in git)
│   ├── SOURCES.csv          manifest: every library file with URL and SHA-256
│   ├── fetch.py             downloads the library again
│   └── LIBRARY.md           the reference library's own README
├── gen/                     schematic generators, build checks, audits, cost model
│   └── data/                prices, estimates, volume factors, pin ledgers, review findings
├── sim/                     design calculations and simulations (numpy, scipy, ngspice)
│   ├── data/                device and supplier surveys
│   ├── spice/               ngspice decks
│   └── out/                 one folder per study: report, spec JSON, plots
├── hardware/                generated KiCad 10 projects with PDF, netlist, ERC and report per board
└── bom/                     generated BOMs, costed BOMs and COST.md

📚 Documentation

	Page	What it answers
01	Overview	the product family, the roadmap, the decision timeline, status
02	Architecture	how the cost-first module is built: blocks, barriers, boards
03	Power stage	the converter phases, devices, gate drive and losses
04	Protection and safety	trips, contactors, fuses, insulation; hardware against firmware
05	Control and firmware	control loops, MPPT, protection timing, the controller
06	Magnetics	inductors, transformers, chokes and how they were verified
07	Sourcing and cost	makers and evidence, cost per module, the benchmark
08	Verification	build checks, audits, reviews — and what is not verified
09	PCS-P125	the DC-to-AC battery inverter, three- and four-wire, with its start-up from the grid
10	DAB-D60	the isolated DC/DC
11	Comparison with Megarevo	row by row against the PMD-75-G3 and the PMA0125; the module-parity register; cost against the benchmark
12	Risks and open items	every open risk, ranked, with what would close it
13	Repository guide	build, simulate, re-cost; conventions for parts and boards
	Glossary · Decisions	terms and abbreviations · digest of the decision register

---

Important

Honesty boundary. Nothing in this repository has been built, bought, quoted or measured. Efficiencies, temperatures and margins are calculated or simulated; prices are catalogue readings (the LCSC readings are a snapshot of 2026-10-05) or estimates; competitor figures are published and unverified by us. A review finding marked closed is a corrected calculation, not a test. Several standard values are transcribed from memory and still have to be checked against the purchased standards. Scope is schematic + BOM + simulation — no PCB layout, mechanics or firmware.

Warning

Top open risks — the full ranked register is in Risks and open items.

1. No supplier quotations. About two thirds of the PV-P75 BOM (66 % of the catalogue total) is engineering estimate, and the 800 USD budget is not met (D-052).
2. The Chinese 1700 V SiC device (Sichain SG2M040170HJ) publishes no qualification, short-circuit or cosmic-ray data; its LCSC price is now read (5.07 USD at 90+, D-069) but not quoted; PV-P75 uses 24, PCS-P125 36, PCS-P125-4W 48 (D-043, D-053).
3. Insulation rests on standard values from memory and an unverified surge-arrester credit; the gate driver's impulse rating needs that credit (D-032, D-043).
4. Gate-drive margins for false turn-on and short-circuit turn-off rest on estimated loop inductances and assumed device withstand times — the double-pulse test is the first bench item (D-028); on the inverter it must include the trip's turn-off near 520 A / 1,050 V (1,437 V calculated against 1,445 V) and short-circuit survival stays a hardware release gate (D-078).
5. Requirements the calculations contradict: PCS-P125's full load from 600 V at 400 V ±15 % (AC-02) is not reachable, PV-P75's 75 kW at 550 V needs 136.4 A against 135 A (75 kW from 556 V; 74.25 kW at 550 V × 135 A), and PV-P110's 110 kW is a PV-input rating — owner's decisions (Risks, group G); the inverter's −30 °C now holds as standby or a small passive table only (rated from −10 °C at power, D-081).

🗺️ What comes next

• PV-P75 boards: drawn (PV-PWR rev A2, PV-CTL rev A2), reviewed and corrected (D-065, D-072); the control board gained the recorder flash, the chainable stop, a ready permissive, a battery-fault input and a status relay, with Ethernet as a footprint option (D-075); the DESAT string re-rated to two 1,300 V diodes per channel (D-081); BOM 980 USD at catalogue prices, 820 USD at 5,000 units. Next: the TLV9024's rejection measured at 3.3 V and 10 ppm/K ladder resistors (risk C9), the insulation audit extended to the cost-first boards, supplier quotations for the largest estimates, a sample set of the re-wound auxiliary transformer (D-076).
• PCS-P125 and PCS-P125-4W: both builds drawn and costed — 1,589 / 1,349 USD three-wire, 1,926 / 1,636 USD four-wire (catalogue / 5,000 units) (D-074). Closed on 2026-10-06: the start-up from the grid (risk F8: AC tap and AC precharge on both builds), the four-wire build (risk F9: a fourth leg, not a midpoint neutral), Ethernet for the EMS and the recorder flash for the fault recorder and the authenticated upgrade (D-075), the auxiliary supply's live winding (D-076), the neutral-leg loop and the ride-through limiter (D-077). Corrected by the re-check R2 on 2026-10-07: the trip chain at its real gates-off current with R_G,off 8.75 Ω, the backup band below the L1 knee, the SiC acceptance and per-lot derating, one coil contract and the residual-current contract (D-078); the tolerance regression, the bounded off-grid transients, ride-through without derating and the repaired AC-start machine (D-079). Corrected by the re-check R3 the same day: the synchronised close one coil at a time, the four-wire short against both trip layers, the coupled PCS / PV bus coordination, two SiC module grades with full tier tables, the off-grid envelope as requirement AC-04 (D-080). Answered after the economical re-check R4: the DESAT string re-rated (1,300 V diodes), the cable-aware DC-bus window enforced with a harness contract, AC-04 as a declared output capability with a release sequence, the cold rating at −10 °C inlet with the passive table and its firmware rule, grade B's 124.57 kW, the magnetics RFQ index (D-081). Still open: the owner's decision on AC-02 and the owner's confirmation of AC-04 and of the −10 °C cold rating (both by delegation); the hardware gates of D-078 (short-circuit survival, the first-article L(I) test to 600 A, a double-pulse test near 520 A / 1,050 V, Sichain's R_DS(on) distribution, which now decides the grade mix); the bench confirmation of the ride-through margin (20.5 A net of noise), the four-wire short's 13.3 A and the coupled-bus peaks; the new DESAT diode's V_F, per-diode split and second source; an agreed load specification per managed island; a cold-rated fan from an RFQ; the magnetics quotations (18 RFQ rows still without a number); data sheets for the RFQ parts (AC contactor coil module, the 4-pole contactors, the type-B residual-current monitor, the four-bar CM choke, the precharge resistors); the L-N surge level (a 3+1 arrangement needs a GDT data sheet); pairing the DC-component measurement on one ADC; the CH9121T's supply current and stock; no spare GPIO on the inverter's controller; powder-core inductors and the stud count as cost levers.
• DAB-D60: the device study is corrected (D-068); drawing a board for it is the owner's decision (DAB-12); otherwise redraw the board cost-first (ARCHITECTURE-COSTFIRST §16).
• Comparison with Megarevo: the rows below the published tables — PV-P75: cold limit, altitude and standby; PCS-P125: the 3W+PE DC window (two rows), cold limit and altitude (Comparison). The altitude option (15 mm isolators for 3,000 m full / 5,000 m derated) is specified and fitted on demand.
• Before any hardware release (outside this repository): double-pulse test of the gate drive, a wound inductor sample, the purchased standards checked against the values used.

_{Scope and rules: CLAUDE.md · requirements: REQUIREMENTS.md · decisions: DECISIONS.md}