RSFF
| Name | Description |
|---|---|
| DW | data width |
| rstValue | reset value |
| Name | Direction | Width | Description |
|---|---|---|---|
| set_in | Input | DW | Set bits of Flip-Flop |
| rst_in | Input | DW | Reset bits of Flip-Flop |
| qout | Output | DW | Output of Flip-Flop |
| CLK | Input | 1 | Clock drives the Flip-Flop |
| RSTn | Input | 1 | Asynchronous reset of Flip-Flop. Active Low |
RS Flip-Flop is the basic element of timing logic, which is mainly used to instantiate the registers. set_in and ret_in are not allowed to be HIGH at the same times or unexpected things may happen.
