First attempt to read the number of actually transferred bytes

v0.3

Added functions needed to access the information about the actual num…

Version with HP0 in 64-bit mode

In this version the HP0 port in Zynq has been switched to the 64-bit mode of operation.
It cured the observed problems with corrupted data.
The data source and AXI DMA remained 32-bit, so the data width translation is handled transparently by the AXI interconnect block.

Version with HP0 in 32-bit mode - reported on Xilinx forum

In this version (design axi_dma_prj1) there were problems with sending the data from PL to PS via HP0.
The problems have been reported in Xilinx forum.