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Modifications
Added possibility to create blocks with all outputs contained in a single record (for groups of registers controlling multiple blocks in parallel).
Such a block must be defined with attribute aggr_outs set to 1, as below:
<block name="SYS1" aggr_outs="1">
The example of system with so defined block may be found in directory "test_ao".
Added possibility to ignore generation of definitions for certain blocks for the particular backend. Now this functionality is used only for Forth. The reason is that J1B embedded CPU has limited memory, that can be easily overflown with definitions of words needed to access all registers and fields in a complex system. Because usually the user needs to access only certain blocks, it is possible to specify the attribute ignore="forth" and skip that particular block. The atribute may be specified either in the definition of the block (igoring all its instances) or in the instantiation of the block, or in the definition of a register.
It is possible to extend that functionality to other backends. However up to now there was no need to do it.
Examples of use:
<block name="SYS1">
<creg name="CTRL" desc="Control register" stb="1" ignore="forth">
<field name="START" width="1" desc="Start the operation"/>
<field name="SPEED" width="4" default="-1" type="signed" desc="Transmission speed"/>
<field name="STOP" width="1" desc="Stop the operation" />
</creg>
<sreg name="STATUS" desc="Status register" ack="1" />
<creg name="ENABLEs" desc="Link enable registers" reps="10" default="0x0"/>
</block>
The register CTRL (with all its bitfields) in all instances of SYS1 block will be ignored in generated Forth code.
<block name="SYS1" ignore="forth">
<creg name="CTRL" desc="Control register" stb="1">
<field name="START" width="1" desc="Start the operation"/>
<field name="SPEED" width="4" default="-1" type="signed" desc="Transmission speed"/>
<field name="STOP" width="1" desc="Stop the operation" />
</creg>
<sreg name="STATUS" desc="Status register" ack="1" />
<creg name="ENABLEs" desc="Link enable registers" reps="10" default="0x0"/>
</block>
All instances of block "SYS1" will be skipped when generating the Forth code.
<block name="MAIN">
<subblock name="LINKS" type="SYS1" reps="NSEL_MAX" ignore="forth" force_vec="1" />
<subblock name="OLINKS" type="SYS1"/>
</block>
The instance "LINKS" will be omitted, but the instance "OLINKS" will be included in the generated Forth code.
Added the attribute "force_vec" that allows implementing the particular instance of the blocks or registers as a vector (even if it has the length of 1). That's useful for parametrized designs, where sometimes the parameter describing the number of implemented registers or blocks may be sometimes equal 1, and sometimes be above 1.
Without that parameter, the implementation of user's code wrapping the generated WB interface depends is different in both above cases.
Example of usage (force_vec="0" is a default, you may skip it):
<blackbox name="EXTHUGE" type="HTEST" addrbits="16" force_vec="0" />
<subblock name="LINKS" type="SYS1" reps="NSEL_MAX" force_vec="1" />
Sometimes you may have different registers with the same names in different blocks. That may result in collision between the names of generated types. To avoid it, you may specify the name of the type that should be generated for the particular register using the "stype" attribute.
Example of usage:
<block name="SYS1">
<creg name="CTRL" desc="Control register" stb="1" stype="t_CTRL_SYS">
<field name="START" width="1" desc="Start the operation" />
<field name="SPEED" width="4" default="-1" type="signed" desc="Transmission speed"/>
<field name="STOP" width="1" desc="Stop the operation" />
</creg>
<sreg name="STATUS" desc="Status register" width="12" type="unsigned" stype="t_STATUS_SYS" ack="1" />
<creg name="ENABLEs" desc="Link enable registers" reps="10" default="0x0"/>
</block>
Special types are defined for simple register "STATUS" and for complex register "CTRL".