Programmer · AI Researcher · Competitive Programmer · Hardware & PCB Designer
Passionate programmer with a strong interest in Artificial Intelligence, focusing on Image Processing and Signal Processing — with a parallel love for digital hardware design (Verilog / FPGA) and PCB design (KiCad → JLCPCB). Currently diving deeper into AI algorithms and continuously expanding my knowledge.
"ไม่เด่น ไม่ดัง จะไม่หันหลังกลับไป" 🔥 — Super AI SS4 Optimizer HeadQuarter
Languages & AI
Hardware, FPGA & PCB
Specialties: Deep Learning · Computer Vision · Signal Processing · Digital Logic Design · Hardware Synthesis · PCB Layout & Routing · Data Analysis & Visualization
| Award | Competition | Venue |
|---|---|---|
| 🥇 Gold | TOI 18 | Chiang Mai University |
| 🥉 Bronze | TOI 17 | Walailak University |
| Place | Hackathon |
|---|---|
| 🥇 1st | Mahidol × SuperAI — Human Activity Recognition |
| 🥈 2nd | Super AI SS5 — Innovation Southern |
| 🥉 3rd | BDI Hackathon |
| 🏅 4th | Burapha × SuperAI — Epidemiology |
| 📑 5th | PSU Phuket — Durian Hackathon |
RTL design and FPGA synthesis on Xilinx hardware:
- 📷 OV7670 Camera Pipeline on Basys3 — grayscale YUV422 capture pipeline with dual-port BRAM, BUFG clocking, and CDC-safe design
- 🧮 CPU & Peripheral Design (Verilog) — UART, AXI protocol, and custom datapath implementation
| Award | Event |
|---|---|
| 🥈 2nd | Digital Design Camp @ TNI |
| 🥈 Silver | TESA Top Gun Rally @ CRMA |
End-to-end board design from schematic capture to manufacturing, using KiCad and fabricated via JLCPCB:
- 🔌 Multi-Port USB Hub — high-speed hub built around the GL3523 controller, with proper USB differential-pair routing and JLCPCB design-rule compliance
- 🧩 Schematic capture · multi-layer layout · impedance-aware routing · DFM for fabrication
💡 Bridging software, FPGA, and physical hardware — from algorithm to silicon to board.
🏆 Viscut Extenshod — The Most Stupid Award