Verification has failed on main branch:
$ make test
iverilog -o test.out src/*.v tests/programcounter_tb.v; vvp ./test.out; rm test.out
src/controller.v:327: warning: Extra digits given for sized binary constant.
src/controller.v:335: warning: Extra digits given for sized binary constant.
src/alu.v:25: error: reg o_flag_c; cannot be driven by primitives or continuous assignment.
src/alu.v:26: error: reg o_flag_z; cannot be driven by primitives or continuous assignment.
2 error(s) during elaboration.
./test.out: Unable to open input file.
rm: cannot remove 'test.out': No such file or directory
Makefile:28: recipe for target 'test' failed
make: *** [test] Error 1
Used icarus version from https://github.com/YosysHQ/oss-cad-suite-build (build 2023-04-28):
$ iverilog -v
Icarus Verilog version 13.0 (devel) (s20221226-126-gb210eb826)
Verification has failed on main branch:
Used icarus version from https://github.com/YosysHQ/oss-cad-suite-build (build 2023-04-28):