[XPU][NIXL] Support GPUDirect RDMA for KV cache transfers#3
Draft
Copilot wants to merge 3 commits into
Draft
Conversation
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
5 tasks
…X commit comment Co-authored-by: zhenwei-intel <109187816+zhenwei-intel@users.noreply.github.com>
Copilot
AI
changed the title
[WIP] Support GPUDirect RDMA in NIXL on XPU
[XPU][NIXL] Support GPUDirect RDMA for KV cache transfers
Feb 25, 2026
2f0f906 to
ff5fcd2
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Enables GPUDirect RDMA for Intel XPU devices in the NIXL KV transfer connector, allowing direct device-to-device KV cache transfers without staging through host memory.
Changes
nixl_connector.py: Add"xpu"to supported KV buffer devices so XPU device memory is used directly for NIXL transfers instead of CPU buffers.vllm/platforms/xpu.py: SetUCX_MEMTYPE_CACHE=nwhenkv_transfer_configis enabled to prevent UCX from misdetecting XPU device memory as host memory. Scoped to KV transfer path only — no effect on non-KV-transfer XPU workloads.tools/install_nixl_from_source_ubuntu.py: Pin UCX to commite5d9887and enable--with-zeat configure time. This is the first UCX revision with Intel Level Zero GPU memory registration support required for XPU GDR. Documented with guidance for future hash updates.Performance
Llama3.3-70B int4, fp8 KV cache, 8×B60, ISL=1500, OSL=150 — under SLO (TTFT<5s, ITL<100ms):
Prerequisite
Requires UCX built from commit
e5d9887or later with--with-ze. The install script handles this automatically.✨ Let Copilot coding agent set things up for you — coding agent works faster and does higher quality work when set up for your repo.