feat: add a systolic array model to buckyball#1
feat: add a systolic array model to buckyball#1daiyongyuan wants to merge 2 commits intoDangoSys:mainfrom
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shirohasuki
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shirohasuki
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Thank you for your contribution, I did a quick review.
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| println!("2x3 * 3x2 matrix multiplication test passed!"); | ||
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this file is too long, please split it
| // Latency parameters | ||
| read_latency: 16.0, // 16 cycles to read data | ||
| compute_latency: 16.0, // 16 cycles for computation | ||
| write_latency: 16.0, // 16 cycles to write results |
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where are these latency from?
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Simulate physical delays in real hardware systems，Op 1 read，Op 2 read，Calculation，Result write
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why is 16 cycles not one. The latency of the SRAM's response to a request is only a few cycles, and the SA is unaware of the memory response latency.
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I know,may be necessary to calculate dynamic latency?
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I believe a simple SA implementation could be written within 300 lines, excluding test code.
shirohasuki
changed the title
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These features have been merged in #3 , close this PR |
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