feat: add a systolic array model to buckyball

bebop/src/arch/buckyball/decoder.rs

@@ -46,7 +46,7 @@ impl DevsModel for Decoder {
     // fence inst dont push to rob
     if funct == 31 {
       FENCE_CSR.store(true, Ordering::Relaxed);
-      self.until_next_event = INFINITY;
+      self.until_next_event = 1.0; // Set to 1.0 to trigger events_int
     } else {
       self.until_next_event = 1.0;
     }
@@ -63,6 +63,14 @@ impl DevsModel for Decoder {
       return Ok(Vec::new());
     }
 
+    // Special handling for Fence instruction (funct=31)
+    if funct == 31 {
+      // Fence instruction has been processed, reset the flag
+      FENCE_CSR.store(false, Ordering::Relaxed);
+      self.until_next_event = INFINITY;
+      return Ok(Vec::new());
+    }
+
     if FENCE_CSR.load(Ordering::Relaxed) {
       self.until_next_event = 1.0;
       return Ok(Vec::new());

bebop/src/arch/buckyball/main.rs

@@ -8,6 +8,7 @@ use super::mem_ctrl::MemController;
 use super::mset::Mset;
 use super::rob::Rob;
 use super::rs::Rs;
+use super::systolic_array::SystolicArray;
 use super::tdma_loader::TdmaLoader;
 use super::tdma_storer::TdmaStorer;
 use super::vecball::VectorBall;
@@ -46,8 +47,10 @@ pub fn create_simulation() -> Simulation {
       Box::new(MemController::new(
         String::from("tdma_mem_write_req"),
         String::from("vball_mem_write_req"),
+        String::from("systolic_mem_write_req"),
         String::from("mem_tdma_read_resp"),
         String::from("mem_vball_read_resp"),
+        String::from("mem_systolic_read_resp"),
         String::from("mem_bank_write_req"),
         String::from("bank_mem_read_resp"),
       )),
@@ -76,6 +79,14 @@ pub fn create_simulation() -> Simulation {
         String::from("commit_to_rob"),
       )),
     ),
+    Model::new(
+      String::from("systolic_array"),
+      Box::new(SystolicArray::new(
+        String::from("systolic_mem_write_req"),
+        String::from("mem_systolic_read_resp"),
+        String::from("commit_to_rob"),
+      )),
+    ),
   ];
 
   let connectors = vec![
@@ -118,13 +129,29 @@ pub fn create_simulation() -> Simulation {
       String::from("vball_mem_write_req"),
       String::from("vball_mem_write_req"),
     ),
+    // Systolic Array <-> MemController (write request)
+    Connector::new(
+      String::from("systolic_memctrl_write_req"),
+      String::from("systolic_array"),
+      String::from("mem_controller"),
+      String::from("systolic_mem_write_req"),
+      String::from("systolic_mem_write_req"),
+    ),
     Connector::new(
       String::from("memctrl_vball_read_resp"),
       String::from("mem_controller"),
       String::from("vector_ball"),
       String::from("mem_vball_read_resp"),
       String::from("mem_vball_read_resp"),
     ),
+    // Systolic Array <-> MemController (read response)
+    Connector::new(
+      String::from("memctrl_systolic_read_resp"),
+      String::from("mem_controller"),
+      String::from("systolic_array"),
+      String::from("mem_systolic_read_resp"),
+      String::from("mem_systolic_read_resp"),
+    ),
     // MemController <-> Bank (write request and read response are multi-cycle)
     Connector::new(
       String::from("memctrl_bank_write_req"),
@@ -169,6 +196,14 @@ pub fn create_simulation() -> Simulation {
       String::from("commit_to_rob"),
       String::from("commit"),
     ),
+    // Systolic Array -> ROB (commit)
+    Connector::new(
+      String::from("systolic_rob_commit"),
+      String::from("systolic_array"),
+      String::from("rob"),
+      String::from("commit_to_rob"),
+      String::from("commit"),
+    ),
   ];
 
   Simulation::post(models, connectors)

bebop/src/arch/buckyball/mem_ctrl.rs

@@ -27,11 +27,13 @@ pub struct MemController {
   // Write request ports (multi-cycle)
   tdma_write_req_port: String,
   vball_write_req_port: String,
+  systolic_write_req_port: String,
   bank_write_req_port: String,
 
   // Read response ports (multi-cycle)
   tdma_read_resp_port: String,
   vball_read_resp_port: String,
+  systolic_read_resp_port: String,
   bank_read_resp_port: String,
 
   until_next_event: f64,
@@ -45,8 +47,10 @@ impl MemController {
   pub fn new(
     tdma_write_req_port: String,
     vball_write_req_port: String,
+    systolic_write_req_port: String,
     tdma_read_resp_port: String,
     vball_read_resp_port: String,
+    systolic_read_resp_port: String,
     bank_write_req_port: String,
     bank_read_resp_port: String,
   ) -> Self {
@@ -56,9 +60,11 @@ impl MemController {
     Self {
       tdma_write_req_port,
       vball_write_req_port,
+      systolic_write_req_port,
       bank_write_req_port,
       tdma_read_resp_port,
       vball_read_resp_port,
+      systolic_read_resp_port,
       bank_read_resp_port,
       until_next_event: INFINITY,
       records: Vec::new(),
@@ -164,6 +170,71 @@ impl DevsModel for MemController {
       return Ok(());
     }
 
+    // Handle write requests from Systolic Array (multi-cycle)
+    if incoming_message.port_name == self.systolic_write_req_port {
+      // Parse request: (rob_id, vbank_id, start_addr, data_u64)
+      // For now, we'll use a simple format where we get the data directly
+      let data: Vec<u64> = 
+        serde_json::from_str(&incoming_message.content)
+        .map_err(|_| SimulationError::InvalidModelState)?;
+      let data_count = data.len();
+
+      // In a real system, we would parse rob_id, vbank_id, start_addr from the request
+      // For now, we'll use hardcoded values for testing
+      let rob_id = 1;
+      let vbank_id = 0;
+      let start_addr = 0;
+
+      // Convert vbank_id to pbank_id using BMT
+      let pbank_id = if let Some(pbank_ids) = get_pbank_ids(vbank_id) {
+        if pbank_ids.is_empty() {
+          vbank_id
+        } else {
+          pbank_ids[0]
+        }
+      } else {
+        vbank_id
+      };
+
+      // Check dependency
+      if scoreboard::check_dependency(pbank_id, rob_id) {
+        // No dependency, can proceed immediately
+        // Re-encode with rob_id, vbank_id, and start_addr for the write request queue
+        let request = (rob_id, vbank_id, start_addr, data);
+        let request_content = serde_json::to_string(&request)
+          .map_err(|_| SimulationError::InvalidModelState)?;
+
+        self
+          .write_request_queue
+          .push(("systolic".to_string(), request_content));
+      } else {
+        // Has dependency, add to scoreboard
+        // Re-encode with rob_id, vbank_id, and start_addr for the scoreboard
+        let request = (rob_id, vbank_id, start_addr, data);
+        let request_content = serde_json::to_string(&request)
+          .map_err(|_| SimulationError::InvalidModelState)?;
+
+        scoreboard::add_to_scoreboard(
+          rob_id,
+          pbank_id,
+          "systolic".to_string(),
+          request_content,
+        );
+      }
+
+      self.records.push(ModelRecord {
+        time: services.global_time(),
+        action: "enqueue_systolic_write".to_string(),
+        subject: format!(
+          "rob_id={}, bank={}, addr={}, count={}",
+          rob_id, vbank_id, start_addr, data_count
+        ),
+      });
+
+      self.until_next_event = 1.0;
+      return Ok(());
+    }
+
     // Handle read responses from Bank - forward to the correct source (multi-cycle)
     if incoming_message.port_name == self.bank_read_resp_port {
       let data_vec: Vec<u128> =
@@ -193,8 +264,10 @@ impl DevsModel for MemController {
     if let Some(resp) = READ_RESPONSE_QUEUE.lock().unwrap().pop() {
       let response_port = if resp.source == "tdma" {
         self.tdma_read_resp_port.clone()
-      } else {
+      } else if resp.source == "vecball" {
         self.vball_read_resp_port.clone()
+      } else {
+        self.systolic_read_resp_port.clone()
       };
 
       messages.push(ModelMessage {

bebop/src/arch/buckyball/mod.rs

@@ -7,6 +7,7 @@ pub mod mset;
 pub mod rob;
 pub mod rs;
 pub mod scoreboard;
+pub mod systolic_array;
 pub mod tdma_loader;
 pub mod tdma_storer;
 pub mod vecball;

bebop/src/arch/buckyball/rs.rs

@@ -6,6 +6,7 @@ use sim::utils::errors::SimulationError;
 use std::f64::INFINITY;
 
 use super::mset::{receive_mset_inst, MSET_INST_CAN_ISSUE};
+use super::systolic_array::{receive_systolic_array_inst, SYSTOLIC_ARRAY_INST_CAN_ISSUE};
 use super::tdma_loader::{receive_mvin_inst, MVIN_INST_CAN_ISSUE};
 use super::tdma_storer::{receive_mvout_inst, MVOUT_INST_CAN_ISSUE};
 use super::vecball::{receive_vecball_inst, VECBALL_INST_CAN_ISSUE};
@@ -87,6 +88,29 @@ impl DevsModel for Rs {
             receive_vecball_inst(inst.xs1, inst.xs2, inst.rob_id);
           }
         },
+        32 => {
+          // Systolic array matrix multiplication instruction
+          // For now, we'll use xs1, xs2, and domain_id to encode the bank IDs and dimensions
+          // In a real system, these would be extracted from register values or immediate fields
+          if SYSTOLIC_ARRAY_INST_CAN_ISSUE.load(Ordering::Relaxed) {
+            let op1_bank_id = inst.xs1;
+            let op2_bank_id = inst.xs2;
+            let wr_bank_id = (inst.domain_id >> 24) & 0xFF;
+            let m_dim = (inst.domain_id >> 16) & 0xFF;
+            let n_dim = (inst.domain_id >> 8) & 0xFF;
+            let k_dim = inst.domain_id & 0xFF;
+
+            receive_systolic_array_inst(
+              op1_bank_id, 
+              op2_bank_id, 
+              wr_bank_id, 
+              m_dim, 
+              n_dim, 
+              k_dim, 
+              inst.rob_id
+            );
+          }
+        },
         _ => {
           return Err(SimulationError::InvalidModelState);
         },