Popular repositories Loading

1. 5-Stage-RISC-Pipelined-Processor 5-Stage-RISC-Pipelined-Processor Public

   This is a 32-bit 5-stage pipelined processor I built from scratch in Verilog. It covers the full standard architecture: Instruction Fetch (IF), Decode (ID), Execute (EX), Memory Access (MEM) and Wr…

   Verilog

2. Verilog_Basic Verilog_Basic Public

   Verilog

3. xls xls Public

   Forked from google/xls

   XLS: Accelerated HW Synthesis

   C++

4. bazel_rules_hdl bazel_rules_hdl Public

   Forked from hdl/bazel_rules_hdl

   Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

   Starlark

5. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

   Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

   OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

   Verilog