🚀 Advanced RTL Design Library

A high-performance, open-source library of industry-standard Verilog IP cores. Unlike traditional beginner labs, this repository focuses on scalable, parameterized, and synthesis-ready hardware design using modern dataflow and behavioral modeling techniques.

⚡ Built for hardware engineers, ASIC/FPGA designers, and anyone looking to understand optimized digital logic, timing, and professional verification practices.

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📦 What’s Inside?

• ✅ Unified IP Cores: Consolidated modules for Combinational (CLA, Encoders, MUXes) and Sequential (Parametrized Counters, Universal Shift Registers) logic.
• 🧪 Self-Checking Testbenches: Exhaustive, automated verification environments that flag errors instantly instead of relying on manual waveform inspection.
• 🚀 High-Speed Architecture: Implementations optimized for minimal gate delays (e.g., Carry Lookahead Adders over Ripple Carry).
• ⚙️ Industry Practices: Features active-low asynchronous resets (rst_n), named port mapping, and ternary dataflow logic.
• 📁 Lean Structure: No cluttered files. Every concept is grouped logically into master core files.

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📂 Directory Overview

Verilog_Basic/
├── basic_gates.v
├── basic_gates_tb.v
├── Combinational/                   # Combinational Logic Cores
│   ├── Adder_Subtractor using MUX/  
│   │   ├── adder_subtractor4.v
│   │   └── adder_subtractor4_tb.v
│   ├── Carry Lookahead Adder/       
│   │   ├── cla4.v
│   │   └── cla4_tb.v
│   ├── decoder3x8/                  
│   │   ├── decoder3x8.v
│   │   └── decoder3x8_tb.v
│   ├── encoder8x3/                  
│   │   ├── encoder8x3.v
│   │   └── encoder8x3_tb.v
│   ├── full_adder/                  
│   │   ├── full_adder.v
│   │   └── full_adder_tb.v
│   └── mux8x1/                      
│       ├── mux8x1.v
│       └── mux8x1_tb.v
├── Sequential/                      # Sequential Logic & State Machines
│   ├── COUNTER/                     
│   │   ├── 2Bit_Counter/
│   │   ├── MOD 6 Counter/
│   │   ├── Ring Counter/
│   │   └── johnson_counter_4bit/
│   ├── FLIP FLOPS/                  
│   │   ├── D Flip Flop/
│   │   ├── JK Flip Flop/
│   │   ├── SR Flip Flop/
│   │   └── T Flip Flop/
│   ├── Finite State Machines/       # Advanced System Controllers
│   │   ├── alu_8bit.v
│   │   ├── traffic_controller_4way.v
│   │   └── uart_full.v
│   ├── SEQUENCE DETECTORS/          # Pattern Recognition (1011)
│   │   ├── Mealy/
│   │   │   └── sd1011_mealy.v
│   │   └── Moore/
│   │       └── moore_1011.v
│   └── SHIFT REGISTERS/             # Data Conversion
│       ├── pipo_shift_register.v
│       ├── piso_shift_register.v
│       ├── sipo_shift_register.v
│       └── siso_shift_register.v
└── README.md                        # Repository documentation