A LoRa header raises HeaderValid alone

[A13xB0]

Fixes #4.

What this changes

• The header is raised as HeaderValid alone. SyncWordValid is the GFSK modem's interrupt (DS_SX1261-2, table 13-29: bit 3, FSK); a LoRa receiver reports the header through HeaderValid. This model only has a LoRa data path, so there is no FSK case to keep. The carrier-gone clear drops the bit too, since nothing raises it now.
• vsx_counters.irq_suppressed says what it counts: one per event, however many of that event's bits were masked.
• Two comments from HeaderValid waits for the preamble, the SFD and the header block #3 now give the right figures: for MeshCore's 32-symbol preamble the fixed twelve symbols were 32.25 symbols early and left a fifth of the PreambleDetected-to-HeaderValid stretch, not a third. The test comment's sixteen-symbol preamble is the chip's default, not MeshCore's.

No ABI change.

Effect on the #745 figures

Expected, from the per-frame counts in the new test and not yet rerun end to end: on the three-node link (12 packets), 1.17 (IrqMask 0x0276) should count 0 suppressed rather than 12, and 1.16 (0x0272) 12 (PreambleDetected) rather than 24.

Verification

• STRICT=1 ./build.sh: 7 test binaries, 0 failures. ./build.sh sanitize: 7, 0 failures. STRICT=1 ./build.sh shared: builds.
• clang-format 18.1.8 --dry-run --Werror include/*.h src/*.h src/*.cpp test/*: clean.
• New case in test_interrupts.cpp, two frames each: mask 0x0276 leaves irq_suppressed at 0, mask 0x0272 counts exactly 2. Both fail against main.
• test_reception.cpp now asserts SyncWordValid is clear while HeaderValid is set. Fails against main.

CI

house rules fails on main already: src/VirtualSX1262.h is 512 lines, over the 500 limit, since #2. This PR does not touch that file. consumers are up to date fails until meshcore-native moves its pin.