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fix(intrinsics): admit scalar math on sm_75 - #1670
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praveenperera wants to merge 3 commits into
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The scalar_math recipe floored every F32/F64 form at PTX 7.0 / sm_80, so `ex2_approx_f32`, `rcp_rn_f32`, `sqrt_rn_f32` and the rest failed target gating on sm_75. The PTX ISA admits all 40 forms on sm_20 or older, except `tanh.approx.f32` at PTX 7.0 / sm_75. sm_75 is also the oldest target CUDA 13 ptxas assembles, so it is the lowest floor the evidence can attest. The family floor is now PTX 7.0 / sm_75, matching `ex2_approx_f16`. The LLVM evidence is re-probed at sm_75 / +ptx70 with the pinned llc and ptxas 13.3.73. The libNVVM evidence is re-captured at compute_75, assembled with ptxas 13.3.33 and linked with nvJitLink at sm_75. The regenerated outputs change only the scalar_math floors and the catalog digest banners. A generator test pins the sm_75 floor and rejects sm_80 and sm_72. A codegen test checks every scalar_math target on both backends and the `ex2_approx_f32` repro at CUDA_OXIDE_TARGET=sm_75. The new scalar_math_sm75 example calls all 40 forms and checks them against the PTX ISA error bounds. examples-compile builds it at sm_75 as PTX and as a libNVVM + nvJitLink cubin. scalar_arithmetic keeps its sm_80 floor here; NVIDIA#1512 covers it. Refs NVIDIA#1462 Signed-off-by: Praveen Perera <me@praveenperera.com>
praveenperera
requested review from
binarybana,
cryos,
elibol,
kkraus14,
roivanov and
rparolin
as code owners
October 29, 2026 20:45
nihalpasham
added
cuda-oxide
Signed-off-by: nihalpasham <nihalp@nvidia.com>
nihalpasham
previously approved these changes
Nov 3, 2026
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/ok to test 105c3a5 |
Collaborator
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Thanks, lowering the 40 At |
scalar_math_sm75's Cargo.lock resolved bytemuck 1.25.2 and bytemuck_derive 1.12.1, while every other example pins 1.25.0 and 1.10.2, so sync-example-locks.sh --check failed. Align it with --align. The regenerated catalog hashes to 21388d23, so the mlir-dialects page stamp moves with it. The floor changes leave the counts it guards as they were: 589 operations and 1058 catalog entries. Signed-off-by: Praveen Perera <me@praveenperera.com>
Contributor
Author
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Thanks! The two failing checks were mechanical, fixed in
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What This PR Does
Lowers the PTX and compute-capability floor of the 40
f32/f64scalar_mathintrinsics (sin_approx_f32,cos_approx_f32,ex2_approx_f32,lg2_approx_f32,rcp_*,rsqrt_*,sqrt_*,tanh_approx_f32) from(PTX 7.0, sm_80)to(PTX 7.0, sm_75)(Turing), re-records LLVM (rust-llvm-23.1.3) andlibNVVM(cuda-13.3) evidence atsm_75, and adds thescalar_math_sm75GPU validation example.Verification
RTX 5090,sm_120a):cargo oxide run scalar_math_sm75 --arch sm_75verifies all 40scalar_mathforms against PTX ISA error bounds (compute-sanitizer --tool memcheck:0 errors).cargo run -p cuda-intrinsics-gen -- check,cargo test -p cuda-intrinsics-gen -p cuda-oxide-codegen --all-targets,just fmt-check,cargo clippy, and repository guards all pass.Part of #1462