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TAPR
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Bring over ringof/dev: design + 3D + mechanical/viewer + CI
- #58
#58
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Bring over ringof/dev: design + 3D + mechanical/viewer + CI
#58
ringof
wants to merge 26 commits into
dev
TAPR/TAPRx888:dev
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design
TAPR/TAPRx888:design
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Commits
Commits on Jul 18, 2026
throwaway: exercise design -> dev pipeline (safe to delete)
David Goncalves
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6bd5f1e
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Merge branch 'dev' into design
ringof
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571d8ba
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Merge branch 'dev' into design
ringof
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7bebec0
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Commits on Jul 26, 2026
Bring over ringof/dev (tranche 2, stage 1): design, library, 3D, board CI & docs
David Goncalves
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b480fe3
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Bring over ringof/dev (tranche 2, stage 2): mechanical enclosure + 3D viewer
David Goncalves
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255bd36
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run_checks: hard-fail the 3D-model check regardless of ENFORCE
David Goncalves
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d5065f9
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Commits on Jul 28, 2026
Improved 3D viewer (#59)
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Commits on Jul 29, 2026
fix BAV99 value, TIS exclude from BOM
David Goncalves
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f355102
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open ERC/DRC to lower severity reporting
David Goncalves
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ae42987
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update CI output on severity reporting
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b5383a3
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Reconcile library/schematic/board drift (ERC/DRC clean at full severity)
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93892c4
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fix orientation error for J1-J4
David Goncalves
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921b073
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Commits on Jul 30, 2026
Add JLCPCB 6-layer DRC rules; refill zones in dev-checks
David Goncalves
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d33392b
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Nudge different-net vias to meet JLC 0.5mm hole-to-hole
David Goncalves
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6fe387c
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Fix SC-70-6 mask slivers; min-web 0.1mm; error-clean DRC
David Goncalves
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291d4ff
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Commits on Jul 31, 2026
interim silkscreen warning-level DRC violations cleanup
David Goncalves
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3033a14
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interim silkscreen warning-level DRC violations cleanup pt. 2
David Goncalves
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fe44b41
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Commits on Aug 2, 2026
interim commit detailed silk/footprint clearance rules, beginning of uVia to regular drill transition
David Goncalves
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cc221a1
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enable missing courtyard as 'warning' AND set logos as exempt from courtyard requirement
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0897bdb
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fix U19 3D model alignment
David Goncalves
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cbb070e
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fix X1 3D model alignment
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0142fa6
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fix D1 3D model alignment
David Goncalves
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34548ce
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fix D3 3D model alignment
David Goncalves
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70e3f5f
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1-6 uVia to std via transition pt 2
David Goncalves
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3e74bff
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refdes and silk cleanup, now produces a zero ERC/DRC error, zero DRC warning output
David Goncalves
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aff50e8
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Commits on Aug 3, 2026
last cleanup of refdes, addition of USB3, USB2 net classes for DRC checks on PCB
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ee02552
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David Goncalves