fixed ORFS flow variables for AutoTuner

docs/user/FlowVariables.md

@@ -296,7 +296,7 @@ configuration file.
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| 0|
 | <a name="SKIP_VT_SWAP"></a>SKIP_VT_SWAP| Do not perform VT swap to improve QoR (default: do VT swap).| |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
-| <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
+| <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| 0|
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically.| |
 | <a name="SYNTH_CANONICALIZE_TCL"></a>SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| |
@@ -313,15 +313,15 @@ configuration file.
 | <a name="SYNTH_MOCK_LARGE_MEMORIES"></a>SYNTH_MOCK_LARGE_MEMORIES| Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. Yosys will generally infer memories from behavioral Verilog code, whether the memories are in standalone modules or instantiated within some larger module. fakeram and empty Verilog memories(blackboxes) of memories will not be inferred memories by Yosys and are therefore not affected by this variable. This is useful and convenient to separate the concern of instantiating and placing memories from investigating other issues with a design, though it comes at the expense of the increased accuracy that using realistic fakemem would provide. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues. This can be especially useful during development of designs where the behavioral model comes first and suitable memories are matched up when the design RTL is stable. A typical use case would be Chisel which will generate a behavioral model for a memories with the required clocks, ports, etc. in addition to a computer readable file with the specification of the memories that is used to [automatically](https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html/) match up suitable memory macros later in the flow. During an architectural screening study, a large range of memory configurations can be investigated quickly with this option, without getting bogged down in the concern of how to realize the memories in silicon for emphemral RTL configurations that exist only long enough to run through the ORFS flow to create a table of some characteristics of a design configuration.| 0|
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
 | <a name="SYNTH_OPERATIONS_ARGS"></a>SYNTH_OPERATIONS_ARGS| Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.| |
-| <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| |
+| <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| 0|
 | <a name="SYNTH_REPEATABLE_BUILD"></a>SYNTH_REPEATABLE_BUILD| License to prune anything that makes builds less repeatable, typically used with Bazel to ensure that builds are bit-for-bit identical so that caching works optimally. Removes debug information that encodes paths, timestamps, etc.| 0|
 | <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion  # 8080.| |
 | <a name="SYNTH_SKIP_KEEP"></a>SYNTH_SKIP_KEEP| Only meaningful together with SYNTH_CHECKPOINT. When set, signals that the supplied checkpoint is still canonical RTLIL (coarse synth and `keep_hierarchy` have not been run yet), so synth.tcl runs the full coarse+fine synthesis flattened. When unset and SYNTH_CHECKPOINT is used, synth.tcl assumes the checkpoint already has coarse synth + `keep_hierarchy` done and resumes from `coarse:fine`.| 0|
 | <a name="SYNTH_SLANG_ARGS"></a>SYNTH_SLANG_ARGS| Additional arguments passed to the slang frontend during synthesis.| |
 | <a name="SYNTH_USE_SYN"></a>SYNTH_USE_SYN| If set to 1, run synthesis using the "syn" tool built into OpenROAD (the synth_syn.tcl flow) instead of the default Yosys-based flow. Defaults to 0 (Yosys flow).| 0|
 | <a name="SYNTH_WRAPPED_ADDERS"></a>SYNTH_WRAPPED_ADDERS| Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.| |
 | <a name="SYNTH_WRAPPED_MULTIPLIERS"></a>SYNTH_WRAPPED_MULTIPLIERS| Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.| |
-| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
+| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| 0|
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| |
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |

flow/scripts/floorplan.tcl

@@ -145,7 +145,7 @@ if { !$::env(SKIP_REPAIR_TIE_FANOUT) } {
   log_cmd repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
 }
 
-if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
+if { [env_var_equals SWAP_ARITH_OPERATORS 1] } {
   # Enable sanity checker until replace_arith_modules becomes stable
   set_debug_level ODB replace_design_check_sanity 1
   log_cmd replace_arith_modules

flow/scripts/resize.tcl

@@ -15,7 +15,7 @@ if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } {
   log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO)
 }
 
-if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
+if { [env_var_equals SWAP_ARITH_OPERATORS 1] } {
   # Enable sanity checker until replace_arith_modules becomes stable
   set_debug_level ODB replace_design_check_sanity 1
   replace_arith_modules

flow/scripts/synth.tcl

@@ -104,7 +104,7 @@ if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
   set synth_full_args [concat $synth_full_args \
     "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
 }
-if { [env_var_exists_and_non_empty SYNTH_OPT_HIER] } {
+if { [env_var_equals SYNTH_OPT_HIER 1] } {
   set synth_full_args [concat $synth_full_args -hieropt]
 }
 
@@ -187,8 +187,8 @@ if { [env_var_exists_and_non_empty SYNTH_RETIME_MODULES] } {
 }
 
 if {
-  [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
-  [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+  [env_var_equals SYNTH_WRAPPED_OPERATORS 1] ||
+  [env_var_equals SWAP_ARITH_OPERATORS 1]
 } {
   source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
 } else {
@@ -211,10 +211,10 @@ opt -purge
 if {
   [env_var_exists_and_non_empty ADDER_MAP_FILE] &&
   (
-    (![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] &&
-      ![env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]) ||
-    (([env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
-        [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]) &&
+    (![env_var_equals SYNTH_WRAPPED_OPERATORS 1] &&
+      ![env_var_equals SWAP_ARITH_OPERATORS 1]) ||
+    (([env_var_equals SYNTH_WRAPPED_OPERATORS 1] ||
+        [env_var_equals SWAP_ARITH_OPERATORS 1]) &&
       ![design_has_extracted_operators])
   )
 } {
@@ -274,8 +274,8 @@ opt
 setundef -zero
 
 if {
-  ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] &&
-  ![env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+  ![env_var_equals SYNTH_WRAPPED_OPERATORS 1] &&
+  ![env_var_equals SWAP_ARITH_OPERATORS 1]
 } {
   log_cmd abc {*}$abc_args
 } else {
@@ -311,8 +311,8 @@ tee -o $::env(REPORTS_DIR)/synth_stat.txt stat -hierarchy {*}$lib_args
 # check the design is composed exclusively of target cells, and
 # check for other problems
 if {
-  ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] &&
-  ![env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+  ![env_var_equals SYNTH_WRAPPED_OPERATORS 1] &&
+  ![env_var_equals SWAP_ARITH_OPERATORS 1]
 } {
   check -assert -mapped
 } else {

flow/scripts/util.tcl

@@ -214,8 +214,8 @@ proc source_env_var_if_exists { env_var } {
 # will be default and this code will be deleted.
 proc hier_options { } {
   if {
-    ([env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
-      [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]) &&
+    ([env_var_equals SYNTH_WRAPPED_OPERATORS 1] ||
+      [env_var_equals SWAP_ARITH_OPERATORS 1]) &&
     !$::env(OPENROAD_HIERARCHICAL)
   } {
     error "SYNTH_WRAPPED_OPERATORS or SWAP_ARITH_OPERATORS require OPENROAD_HIERARCHICAL to be set."

flow/scripts/variables.yaml

@@ -467,6 +467,7 @@ SYNTH_WRAPPED_OPERATORS:
     the flow.
   stages:
     - All stages
+  default: 0
 SYNTH_WRAPPED_ADDERS:
   description: >
     Specify the adder modules that can be used for synthesis, separated by commas.
@@ -484,6 +485,7 @@ SWAP_ARITH_OPERATORS:
     Improve timing QoR by swapping ALU and MULT arithmetic operators.
   stages:
     - All stages
+  default: 0
 FLOORPLAN_DEF:
   description: |
     Use the DEF file to initialize floorplan. Mutually exclusive with FOOTPRINT or DIE_AREA/CORE_AREA or CORE_UTILIZATION.
@@ -1074,6 +1076,7 @@ SYNTH_OPT_HIER:
     Optimize constants across hierarchical boundaries.
   stages:
     - synth
+  default: 0
 VERILOG_TOP_PARAMS:
   description: |
     Apply toplevel params (if exist). Passed in as a list of key value pairs